초록 ▼

An improved duty cycle timer provides a duty cycle control signal having alternate “on”and “off”intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counte

An improved duty cycle timer provides a duty cycle control signal having alternate “on”and “off”intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the “off”interval and the other counter measures the “on”interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the “off”interval is longer than the “on”interval. Associated “hold”circuitry is operative to suspend operation of the duty cycle timer when some particular demand is satisfied, but resumes operation of the timer from where it stopped when the particular demand returns.

대표청구항 ▼

An improved duty cycle timer for providing a duty cycle control signal, said duty cycle control signal having alternate “on”and “off”intervals of different logic states, said timer comprising: integrated circuit means including first clock signal generating means for generating a first frequency clo

An improved duty cycle timer for providing a duty cycle control signal, said duty cycle control signal having alternate “on”and “off”intervals of different logic states, said timer comprising: integrated circuit means including first clock signal generating means for generating a first frequency clock, second clock signal generating means for generating a second frequency clock independent of said first clock, first electronic counting means responsive to said first clock for measuring a predetermined one of said “on”and “off”time intervals and providing a signal representative of the completion thereof, and second electronic counting means responsive to said second clock for measuring the other one of said “on”and “off”time intervals and providing a signal representative of the completion thereof, said first and said second clock signal generating means each being responsive to a two-state “enable or hold”signal to respectively enable or inhibit operation of the respective said clock signal generating means, any count in said first and said second counting means remaining static during application of said “hold”signal thereto; means for connecting a two-state “enable or hold”signal to said first and second clock signal generating means and having an input terminal adapted to have an AC voltage connected thereto and disconnected therefrom and including rectifying means operatively connected to a “hold”potential and to said first and said second clock signal generating means for applying an “enabling”DC potential to said clock signal generating means when said AC voltage is connected to said input terminal and for applying said “hold”potential to said clock signal generating means when said AC voltage is disconnected from said input terminal; circuit means, including resetting circuitry, cross-connecting said first and said second electronic counting means in complementary relation for initiating said measurement of said “on”and said “off”time intervals respectively from a reset condition of the respective one of said first and said second electronic counting means in response to said signals representative of the completion of the preceding said “off”and “on”time intervals respectively; and wherein said duty cycle control signal is provided by at least one of said first and said second electronic counting means.