$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Token passing network utilizing active node table 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04J-003/26
출원번호 US-0895267 (1986-08-11)
발명자 / 주소
  • Roach J. Monte (Ann Arbor MI) Jones Lester A. (Mentor OH) Van Sickle Wayne C. (South Euclid OH) Schultz Ronald E. (Solon OH)
출원인 / 주소
  • Allen-Bradley Company, Inc. (Milwaukee WI 02)
인용정보 피인용 횟수 : 88  인용 특허 : 0

초록 ▼

A programmable controller is adapted to communicate in a token passing logical ring network in a peer-to-peer fashion. The programmable controller is a station on the network and contains an interface which implements the network protocol. The protocol requires that each station maintain an Active N

대표청구항 ▼

A method for operating a station on a token passing logical ring network, the station including a memory for storing data for use by the station, the method comprising the steps of: (a) receiving messages from the network, said messages containing information fields identifying the source, the desti

이 특허를 인용한 특허 (88)

  1. Uphadya Nagaraja ; Hagglund Barry ; Nguyen Thi, ATM emulated path protection.
    상세보기
  2. Rhodehamel Michael W. ; Sarangdhar Nitin V. ; Pathikonda Chakrapani, Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair.
    상세보기
  3. Huai, Jin; Anbiah, Anix; Baldwin, Gary, Automatic propagation of circuit information in a communications network.
    상세보기
  4. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, Buffer device and method of operation in a buffer device.
    상세보기
  5. Perego, Richard; Ware, Fred; Tsern, Ely, Buffered memory having a control bus and dedicated data lines.
    상세보기
  6. Drehmel, Robert Allen; Haselhorst, Kent Harold; Hoover, Russel Dean; Marcella, James Anthony, Bus architecture employing varying width uni-directional command bus.
    상세보기
  7. Drehmel, Robert Allen; Haselhorst, Kent Harold; Hoover, Russell Dean; Marcella, James Anthony, Bus architecture employing varying width uni-directional command bus.
    상세보기
  8. Nakamura, Masato; Yabusaki, Tatsumi; Sugimoto, Tomitsugu, Communication management apparatus, communication node, and data communication method.
    상세보기
  9. Nakamura, Masato, Communication managing apparatus and data communication method.
    상세보기
  10. Nakazumi Seiji,JPX, Communication network configuration detecting method using frame transmission.
    상세보기
  11. Perego,Richard; Ware,Fred; Tsern,Ely, Configurable width buffered module.
    상세보기
  12. Perego,Richard; Ware,Fred; Tsern,Ely; Hampel,Craig, Configurable width buffered module having a bypass circuit.
    상세보기
  13. Ware,Fred; Perego,Richard; Tsern,Ely, Configurable width buffered module having flyby elements.
    상세보기
  14. Ware,Fred; Perego,Richard; Tsern,Ely, Configurable width buffered module having switch elements.
    상세보기
  15. Farmwald,Michael; Horowitz,Mark, Controller device and method for operating same.
    상세보기
  16. Tomitsuka,Futoshi; Miyake,Takashi, Data communication system, data communication method, and communication unit.
    상세보기
  17. Hasha, Richard L.; Xun, Lu; Kakivaya, Gopala Krishna R.; Malkhi, Dahlia, Data consistency within a federation infrastructure.
    상세보기
  18. Blackmon, Herman Lee; Drehmel, Robert Allen; Haselhorst, Kent Harold; Marcella, James Anthony, Data routing using status-response signals.
    상세보기
  19. Woods, Randy D.; Dupree, Wayne P.; Jachim, David M.; Verniers, Gerrit H.; Churchill, Stephen G.; Fernandez, George P., Distributed computing environment using real-time scheduling logic and time deterministic architecture.
    상세보기
  20. Nanda, Sanjiv; Walton, Jay Rodney, Distributed hierarchical scheduling in an AD hoc network.
    상세보기
  21. Nanda, Sanjiv; Walton, J. Rodney, Distributed hierarchical scheduling in an ad hoc network.
    상세보기
  22. Neuendorff, Keith Eric; Daniel, Philippe J., Generation of synchronous transport signal data used for network protection operation.
    상세보기
  23. Nanda, Sanjiv; Meylan, Arnaud; Walton, Jay Rodney, High speed media access control.
    상세보기
  24. Nanda, Sanjiv; Meylan, Arnaud; Walton, Jay Rodney, High speed media access control.
    상세보기
  25. Walton, Jay Rodney; Nanda, Sanjiv, High speed media access control and direct link protocol.
    상세보기
  26. Walton, Jay Rodney; Nanda, Sanjiv, High speed media access control and direct link protocol.
    상세보기
  27. Walton, Jay Rodney; Ketchum, John W.; Nanda, Sanjiv, High speed media access control with legacy system interoperability.
    상세보기
  28. Fisch Matthew A. ; Rhodehamel Michael W. ; Sarangdhar Nitin, Initialization mechanism for symmetric arbitration agents.
    상세보기
  29. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, Integrated circuit buffer device.
    상세보기
  30. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, Integrated circuit buffer device.
    상세보기
  31. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, Integrated circuit buffer device.
    상세보기
  32. Farmwald, Michael; Horowitz, Mark, Integrated circuit device.
    상세보기
  33. Tsuchiya Paul F. (Washington DC) Kirkman W. Worth (Fairfax VA), Landmark hierarchy method for routing signals in a communications network.
    상세보기
  34. Hasha, Richard L.; Xun, Lu; Kakivaya, Gopala Krishna R.; Malkhi, Dahlia, Maintaining consistency within a federation infrastructure.
    상세보기
  35. Siegel Stuart B. (Canton MI) Marriott Jeffery C. (Ann Arbor MI), Master slave industrial token passing network.
    상세보기
  36. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, Memory module having an integrated circuit buffer device.
    상세보기
  37. Tsern,Ely, Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology.
    상세보기
  38. Farmwald,Michael; Horowitz,Mark, Memory module including an integrated circuit device.
    상세보기
  39. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  40. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  41. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  42. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  43. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  44. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  45. Shaeffer, Ian; Tsern, Ely; Hampel, Craig, Memory system topologies including a buffer device and an integrated circuit memory device.
    상세보기
  46. Nanda, Sanjiv; Walton, Jay Rodney, Method and apparatus for an ad-hoc wireless communications system.
    상세보기
  47. Meylan, Arnaud; Abraham, Santosh, Method and apparatus for scheduling in a wireless network.
    상세보기
  48. Duckwall William S. ; Teener Michael D., Method and apparatus for the addition and removal of nodes from a common interconnect.
    상세보기
  49. Duckwall, William S.; Teener, Michael D., Method and apparatus for the addition and removal of nodes from a common interconnect.
    상세보기
  50. Duckwall, William S.; Teener, Michael D., Method and apparatus for the addition and removal of nodes from a common interconnect.
    상세보기
  51. Duckwall,William S.; Teener,Michael D., Method and apparatus for the addition and removal of nodes from a common interconnect.
    상세보기
  52. Ketchum, John W.; Walton, Jay Rodney; Nanda, Sanjiv, Method and apparatus for wireless LAN (WLAN) data multiplexing.
    상세보기
  53. Johnson ; III Hoke S. (Monte Sereno CA), Method and circuit for decoding a Manchester code signal.
    상세보기
  54. Reichbauer Hermann (Munich DEX) Mueller Rudi (Groebenzell DEX) Riccato Aldo (Munich DEX), Method for forming an address table in a ring-shaped communications network.
    상세보기
  55. Ketchum, John W.; Wallace, Mark S.; Walton, Jay Rodney; Nanda, Sanjiv, Method, apparatus, and system for medium access control.
    상세보기
  56. Ketchum, John W.; Wallace, Mark S.; Walton, Jay Rodney; Nanda, Sanjiv, Method, apparatus, and system for medium access control.
    상세보기
  57. Ketchum, John W.; Walton, Jay Rodney; Nanda, Sanjiv, Method, apparatus, and system for multiplexing protocol data units.
    상세보기
  58. Ketchum, John Wendell; Walton, Jay Rodney; Nanda, Sanjiv, Method, apparatus, and system for multiplexing protocol data units.
    상세보기
  59. Taylor, Alan L.; Haase, David; Brundage, Michael C.; Gulve, Somnath A.; Chinta, Varun K., Method, data storage system and computer program product for managing data copying.
    상세보기
  60. Dewey,Douglas William, Method, system, and program for allocating tasks to a plurality of processors.
    상세보기
  61. Berry Kirk H. (Gaithersburg MD) Mostafa Asghar (Silver Spring MD), Methods and apparatus for allocating time slots and fragments on communications lines between adjacent nodes in a high g.
    상세보기
  62. Amar Singh, Methods and apparatuses for controlling the operation of a digital processing system.
    상세보기
  63. Scott Sarnikowski ; Unmesh Agarwala ; Stanley S. Quan ; Charles E. Comstock ; Frank G. Moore, Multiprocessor system with fiber optic bus interconnect for interprocessor communications.
    상세보기
  64. Takahashi Kousuke (Tokyo JPX), Nest level judging hardware device for high speed message handling systems.
    상세보기
  65. Belschner, Ing Ralf; Hedenetz, Bernd; Temple, Christopher; Schedl, Anton; Berwanger, Josef; Peller, Martin; Führer, Thomas; Millsap, Arnold; Forest, Thomas; Pokorny, Gregor; Fuhrmann, Peter, Network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network.
    상세보기
  66. Iddon Robin A. (Edinburgh GBX) Palmer Peter F. (Midlothian GBX) McBride Richard (Musselburgh GBX) Briggs John (Loanhead GBX), Network data collection method and apparatus.
    상세보기
  67. Nakamura, Masato, Network performance estimating apparatus and network performance estimating method, network configuration checking method, communication managing apparatus, and data communication method.
    상세보기
  68. Critchley, Craig A.; Wortendyke, David A.; Marucheck, Michael J.; Hasha, Richard L., Optimizing access to federation infrastructure-based resources.
    상세보기
  69. Drehmel, Robert Allen; Haselhorst, Kent Harold; Hoover, Russell Dean; Marcella, James Anthony; Nation, George Wayne, Processor-memory bus architecture for supporting multiple processors.
    상세보기
  70. Isaac,Emad; Van Goethem,Tim R.; Ayoub,Ramy P.; D'Avello,Robert F., Rapid vehicle bus network activity.
    상세보기
  71. Meylan, Arnaud; Nanda, Sanjiv, Scheduling with reverse direction grant in wireless communication systems.
    상세보기
  72. Meylan, Arnaud; Nanda, Sanjiv, Scheduling with reverse direction grant in wireless communication systems.
    상세보기
  73. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices.
    상세보기
  74. Takeshi Shimizu JP; Wolf-Dietrich Weber ; Patrick J. Helland ; Thomas M. Wicki ; Winfried W. Wilcke, System and method for acknowledging receipt of messages within a packet based communication network.
    상세보기
  75. Foote Garritt W. ; Mehta Pratik, System and method for providing delayed start-up of an activity monitor in a distributed I/O system.
    상세보기
  76. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices.
    상세보기
  77. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, System featuring a master device, a buffer device and a plurality of integrated circuit memory devices.
    상세보기
  78. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, System featuring memory modules that include an integrated circuit buffer devices.
    상세보기
  79. Perego, Richard E; Sidiropoulos, Stefanos; Tsern, Ely, System having a controller device, a buffer device and a plurality of memory devices.
    상세보기
  80. Perego,Richard E.; Sidiropoulos,Stefanos; Tsern,Ely, System having a controller device, a buffer device and a plurality of memory devices.
    상세보기
  81. Tsern, Ely; Shaeffer, Ian; Hampel, Craig, System including a buffered memory module.
    상세보기
  82. Donnelly,Kevin; Johnson,Mark; Tran,Chanh; Dillon, deceased,John B., Transceiver with latency alignment circuitry.
    상세보기
  83. Donnelly,Kevin; Johnson,Mark; Tran,Chanh; Dillon, legal representative,Nancy D.; Dillon, deceased,John B., Transceiver with latency alignment circuitry.
    상세보기
  84. Donnelly,Kevin; Johnson,Mark; Tran,Chanh; Dillon, legal representative,Nancy D.; Dillon, deceased,John B., Transceiver with latency alignment circuitry.
    상세보기
  85. Abraham, Santosh; Meylan, Arnaud; Walton, Jay Rodney, Transmission mode and rate selection for a wireless communication system.
    상세보기
  86. Van de Steeg, Kerry; Blair, Richard A.; Lee, Kenneth S., Tuning of industrial automation system performance based on device operating characteristics.
    상세보기
  87. Pflaumer Michael W. (Berkeley CA), Variable speed local area network.
    상세보기
  88. Ketchum, John W.; Walton, Jay Rodney; Nanda, Sanjiv, Wireless LAN protocol stack.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로