|국가/구분||United States(US) Patent 등록|
|발명자 / 주소|
|인용정보||피인용 횟수 : 132 인용 특허 : 0|
An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.
A method of operating an electronic computer processor having a plurality of ALU\s which may be operated in combination to increase their effective word length comprising the steps of: (a) synchronizing two or more of said ALU\s; (b) connecting two or more of said ALU\s according to a field in a single instruction word, whereby each group of connected ALU\s and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment; (c) entering a separate operation code and a separate operand instructio...