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특허 상세정보

Processor utilizing reconfigurable process segments to accomodate data word length

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-009/00   
미국특허분류(USC) 364/900
출원번호 US-0817814 (1985-12-26)
발명자 / 주소
인용정보 피인용 횟수 : 132  인용 특허 : 0
초록

An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.

대표
청구항

A method of operating an electronic computer processor having a plurality of ALU\s which may be operated in combination to increase their effective word length comprising the steps of: (a) synchronizing two or more of said ALU\s; (b) connecting two or more of said ALU\s according to a field in a single instruction word, whereby each group of connected ALU\s and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment; (c) entering a separate operation code and a separate operand instructio...

이 특허를 인용한 특허 피인용횟수: 132

  1. Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Kuchinski David Christopher ; Knowles Billy Jack ; Nier Richard Edward ; Retter Eric Eugene ; Richardson Robert Reist ; Rolfe. APAP I/O programmable router. USP1999105963745.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  5. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  6. Hogenauer, Eugene B.. Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks. USP2005036874079.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  11. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  12. Mahan, Justin Michael; Hutchins, Edward A.; Toksvig, Michael J. M.. Address independent shader program loading. USP2015059024957.
  13. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis. Advanced parallel array processor (APAP). USP1998025717943.
  14. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis. Advanced parallel array processor (APAP). USP1998015710935.
  15. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Knowles Billy J. (Kingston NY) Lesmeister . Advanced parallel array processor I/O connection. USP1997045617577.
  16. Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David . Advanced parallel processor including advanced support hardware. USP1996125588152.
  17. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  18. Ahmed, Ashraf; Filippo, Michael A.; Pickett, James K.. Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor. USP2005096944744.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  21. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  22. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  23. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  24. Wilkinson Paul A. (Apalachin NY) Kogge Peter M. (Endicott NY). Array processor dotted communication network based on H-DOTs. USP1997055630162.
  25. Dieffenderfer James Warren ; Kogge Peter Michael ; Wilkinson Paul Amba ; Schoonover Nicholas Jerome. Associative parallel processing system. USP1998105822608.
  26. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. Autonomous SIMD/MIMD processor memory elements. USP1998025717944.
  27. Filippo,Michael A.. Clock control of functional units in an integrated circuit based on monitoring unit signals to predict inactivity. USP2006016983389.
  28. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  29. Wilson, Sophie. Conditional branch instruction capable of testing a plurality of indicators in a predicate register. USP2010127861071.
  30. Wilson,Sophie. Conditional execution per lane. USP2006016986025.
  31. Wilson,Sophie. Conditional execution per lane. USP2007107287152.
  32. Wilson, Sophie. Conditional execution with multiple destination stores. USP2013088521997.
  33. Wilson,Sophie. Conditional execution with multiple destination stores. USP2006107127593.
  34. Karandikar, Ashish; Agarwal, Pooja. Configurable SIMD engine with high, low and mixed precision modes. USP2014058725990.
  35. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  36. Karandikar, Ashish; Gadre, Shirish; Gruner, Frederick R.; Sijstermans, Franciscus W.. Context switching on a video processor having a scalar execution unit and a vector execution unit. USP2013048424012.
  37. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  38. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael ; Lesmeister Donald Michael ; Richardson Robert Reist ; Smoral Vincent John. Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library. USP1998065765012.
  39. Mirsky,Ethan; French,Robert; Eslick,Ian. Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification. USP2007037188192.
  40. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F.. DPGA-coupled microprocessors. USP2000046052773.
  41. Aldrich,Bradley C.; Fridman,Jose; Meyer,Paul; Liang,Gang. DSP execution unit for efficient alternate modes for processing multiple data sizes. USP2006057047271.
  42. Sheng, Chengke. Data processor and methods thereof. USP2010087788471.
  43. Lee, Ki Jun; Kong, Jun Jin; Kim, Yong June; Kim, Jae Hong; Son, Hong Rak; Chung, Jung Soo; Choi, Seong Hyeong. Device and method for processing data including generating a pseudo random number sequence. USP2015109158500.
  44. Sutou, Shin-ichi. Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network. USP2013128607029.
  45. Furukawa, Hiroshi. Enhanced processor element structure in a reconfigurable integrated circuit device. USP2010067734896.
  46. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  47. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  48. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  49. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  50. Gschwind, Michael K.; Olsson, Brett; Salapura, Valentina. Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers. USP2017089727336.
  51. Gschwind, Michael K.; Olsson, Brett; Salapura, Valentina. Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers. USP2017089727337.
  52. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Lesmeister Donald Michael ; Miles Richard Ernest ; Nier Richard Edward ; Richards. Fully distributed processing memory element. USP1999105963746.
  53. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  54. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  55. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  56. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  57. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  58. Andre DeHon ; Ethan Mirsky ; Thomas F. Knight, Jr.. Intermediate-grain reconfigurable processing device. USP2002126496918.
  59. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F.. Intermediate-grain reconfigurable processing device. USP2001076266760.
  60. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F.. Intermediate-grain reconfigurable processing device. USP1999095956518.
  61. DeHon, Andre; Mirsky, Ethan; Knight, Jr., Thomas F.. Intermediate-grain reconfigurable processing device. USP2004016684318.
  62. Crow, Franklin C.; Sewall, Jeffrey R.. Interrupt handling techniques in the rasterizer of a GPU. USP2015069064333.
  63. Crow, Franklin C.; Sewall, Jeffrey R.. Interrupt handling techniques in the rasterizer of a GPU. USP2014078780123.
  64. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D.. Latency tolerant system for executing video processing operations. USP2014048687008.
  65. Mirsky, Ethan; French, Robert; Eslick, Ian. Local control of multiple context processing elements with configuration contexts. USP2004066751722.
  66. Mirsky, Ethan; French, Robert; Eslick, Ian. Local control of multiple context processing elements with major contexts and minor contexts. USP2003046553479.
  67. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  68. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  69. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  70. Mirsky Ethan A.. Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements. USP2001056226735.
  71. Mirsky, Ethan A.. Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements. USP2003076591357.
  72. Mirsky,Ethan A.. Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements. USP2008127464251.
  73. Mirsky Ethan ; French Robert ; Eslick Ian. Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont. USP1999065915123.
  74. Ethan Mirsky ; Robert French ; Ian Eslick. Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements. USP2002096457116.
  75. Mirsky Ethan ; French Robert ; Eslick Ian. Method and apparatus for position independent reconfiguration in a network of multiple context processing elements. USP2000086108760.
  76. Mirsky Ethan ; French Robert ; Eslick Ian. Method and apparatus for retiming in a network of multiple context processing elements. USP2000096122719.
  77. Mirsky, Ethan; French, Robert; Eslick, Ian. Method and apparatus for retiming in a network of multiple context processing elements. USP2003026526498.
  78. Mirsky,Ethan; French,Robert; Eslick,Ian. Method and apparatus for retiming in a network of multiple context processing elements. USP2007097266672.
  79. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  80. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  81. Danskin, John M.; Tamasi, Anthony Michael. Method and system for implementing fragment operation processing across a graphics bus interconnect. USP2015079092170.
  82. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  83. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  84. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  85. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  86. Bowen, Andrew D.. Method and system for non stalling pipeline instruction fetching from memory. USP2014018624906.
  87. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  88. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  89. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  90. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  91. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  92. Karandikar, Ashish; Gadre, Shirish; Salek, Amir H.. Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions. USP2014058738891.
  93. Lew, Stephen D.; Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W.. Multi context execution on a video processor. USP2014038683184.
  94. Gschwind, Michael K.; Olsson, Brett. Multi-addressable register files and format conversions associated therewith. USP2016089411585.
  95. Gschwind, Michael K.; Olsson, Brett. Multi-addressable register files and format conversions associated therewith. USP2016079395981.
  96. Mirsky,Ethan; French,Robert; Eslick,Ian. Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements. USP2006016990566.
  97. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D.; Cheng, Christopher T.. Multidimensional datapath processing in a video processor. USP2013078493396.
  98. Garg, Atul; Sharma, Anil. Multistandard hardware video encoder. USP2014038681861.
  99. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce. N-dimensional modified hypercube. USP1998085794059.
  100. Kanuri, Mrudula. Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory. USP2014038683126.
  101. Knowles Billy J. (Kingston NY) Collins Clive A. (Poughkeepsie NY) Desnoyers Christine M. (Pine Bush NY) Grice Donald G. (Kingston NY) Rolfe David B. (West Hurley NY). Parallel computer system providing multi-ported intelligent memory. USP1997015594918.
  102. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. Parallel processing system having asynchronous SIMD processing and data parallel coding. USP1998065761523.
  103. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. Partitioning of processing elements in a SIMD/MIMD array processor. USP1999035878241.
  104. Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W.; Su, Zhiqiang Jonathan. Pipelined L2 cache for memory transfers for a video processor. USP2015089111368.
  105. Vamanan, Balajee; Methar, Tukaram; Kanuri, Mrudula; Krishnan, Sreenivas. Processing of read requests in a memory controller using pre-fetch mechanism. USP2013078489851.
  106. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  107. Mahan, Justin Michael; Hutchins, Edward A.; Kubalska, Ewa M.; Battle, James T.. Program sequencer for generating indeterminant length shader programs for a graphics processor. USP2014028659601.
  108. Lew, Stephen D.; Gadre, Shirish; Karandikar, Ashish; Sijstermans, Franciscus W.. Programmable DMA engine for implementing memory transfers and video processing for a video processor. USP2014058736623.
  109. Garg, Atul; Venkatapuram, Prahlad. Rewind-enabled hardware encoder. USP2014128923385.
  110. Gschwind, Michael Karl; Hofstee, Harm Peter; Hopkins, Martin Edward. SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode. USP2005016839828.
  111. Ozaki, Tomoaki. SIMD microprocessor, image processing apparatus including same, and image processing method used therein. USP2011118060726.
  112. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. SIMD/MIMD array processor with vector processing. USP1999105966528.
  113. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E. SIMD/MIMD processing memory element (PME). USP1997045625836.
  114. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. SIMD/MIMD processing synchronization. USP2000076094715.
  115. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael. SIMIMD array processing system. USP1998095805915.
  116. Aldrich, Bradley C.; Fridman, Jose; Meyer, Paul; Liang, Gang. Selectively processing different size data in multiplier and ALU paths in parallel. USP2004046725360.
  117. Kawano, Tetsuo; Furukawa, Hiroshi; Kasama, Ichiro; Imafuku, Kazuaki; Suzuki, Toshiaki. Semiconductor device having an arithmetic unit of a reconfigurable circuit configuration in accordance with stored configuration data and a memory storing fixed value data to be supplied to the arithmetic unit, requiring no data area for storing fixed value data to be set in a configuration memory. USP2009087580963.
  118. Mahan, Justin Michael; Hutchins, Edward A.. Shader program instruction fetch. USP2013048411096.
  119. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome. Slide bus communication functions for SIMD/MIMD array processor. USP1998015713037.
  120. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael. Slide network for an array processor. USP1998065765015.
  121. Mahan, Justin Michael; Hutchins, Edward A.. Software assisted shader merging. USP2014048698819.
  122. Su, Zhiqiang Jonathan; Karandikar, Ashish. State machine control for a pipelined L2 cache to implement memory transfers for a video processor. USP2013078493397.
  123. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  124. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D.. Stream processing in a video processor. USP2013048416251.
  125. Hansen, Craig; Moussouris, John; Massalin, Alexia. System and apparatus for group floating-point inflate and deflate operations. USP2014078769248.
  126. Hansen, Craig; Moussouris, John; Massalin, Alexia. System and apparatus for group floating-point inflate and deflate operations. USP2014038683182.
  127. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  128. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  129. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  130. Mirsky, Ethan; French, Robert; Eslick, Ian. Three level direct communication connections between neighboring multiple context processing elements. USP2004066745317.
  131. Luu, Viet-Tam; Pflughaupt, Russell. Validating a graphics pipeline using pre-determined schedules. USP2013048427490.
  132. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D.; Cheng, Christopher T.. Video processor having scalar and vector components. USP2014048698817.