[특허]Data Processor system having look-ahead control

Data Processor system having look-ahead control 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/00
출원번호	US-0792607 (1985-10-29)
우선권정보	JP-0230527 (1984-11-01)
발명자 / 주소	Teshima Tooru (Yokohama JPX) Urushihara Tetsuo (Sagamihara JPX)
출원인 / 주소	Fujitsu Limited (Kawasaki JPX 03)
인용정보	피인용 횟수 : 24 인용 특허 : 0

초록 ▼

A data processor system is set up with, at least, a main memory and a central control unit. The main memory stores therein instructions to be executed by the central control unit. The main memory contains therein an even part buffer and an odd part buffer which momentarily store prefetch instructions of even addresses and odd addresses, respectively. The thus buffered prefetch instructions are sequentially fed from these two buffers alternately to the central control unit.

대표청구항 ▼

A data processor system, comprising: a main memory; and a central control unit, operatively connected to said main memory, the central control unit reading instructions stored in the main memory using addresses having even and odd addresses, executing the read instructions and producing an instruction prefetch starting signal used for initializing an advanced read control in said main memory, every time a discontinuity occurs in a flow of the addresses, such as an address jump, and the instruction prefetch starting signal being issued preceding the issuance of an instruction fetch request; and said main memory comprising: an even memory bank and an odd memory bank which are addressed by the even addresses and odd addresses, respectively, the two memory banks operating independently of each other and operatively connected to said central control unit; an even prefetch instruction buffer and an odd prefetch instruction buffer operatively connected to the even and odd memory banks, respectively, the even and odd prefetch instruction buffers being operatively connected to said central control unit, even supervising circuit means conneced to said central control unit and said even prefetch instruction buffer and odd supervising circuit means connected to said central control unit and said odd prefetch instruction buffer and both for producing resultant supervisory information indicating whether the prefetch instructions are stored in advance in the prefetch instruction buffers, respectively, allowing instruction fetch by the central control unit based only on the instruction fetch request, said main memory reading instructions sequentially from the even and odd memory banks, usings the odd and even addresses from said central control unit, based on said instruction prefetch starting signal and preceding issuance of the instruction fetch request from the central control unit, and storing the read instructions in the corresponding prefetch instruction buffers, and said main memory including a memory control logic circuit, connected to said central control unit and said supervising circuit means, for controlling said main memory, and the memory control logic circuit achieves the advanced read operation of the read instructions from the prefetch instruction buffers in accordance with the resultant supervisory information from the supervising circuits, to store the thus read instructions in said odd and even prefetch instruction buffers and, then feeds the thus stored prefetech instructions from the respective odd and even prefetch instruction buffers to said central control unit in response to the instruction fetch request issued by the central control unit, by controlling the even and off prefetch instruction buffers, in response to the instruction fetch request issued from the central control unit, sich that the stored prefetch instructions are produced alternately from the even and odd prefetch instruction buffers and supplied to the central control unit.

이 특허를 인용한 특허 (24)

Saito Hiroshi,JPX ; Sasaki Takatsugu,JPX ; Sugahara Hirohide,JPX ; Kabemoto Akira,JPX ; Takahashi Hajime,JPX ; Funaki Jun,JPX, Asynchronous access system controlling processing modules making requests to a shared system memory.
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Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Cache allocation policy based on speculative request history.
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Hara Kazuhiko (Sanda JPX) Yamaura Shinichi (Kobe JPX) Yoshioka Keiichi (Sanda JPX) Katayama Takao (Ikeda JPX), Central processing unit including inhibited branch area.
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Lewchuk W. Kurt ; McMinn Brian D. ; Pickett James K., Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation.
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Lewchuk W. Kurt ; McMinn Brian D. ; Pickett James K., Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation.
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Teshome Abeye, Computer with cache-line buffers for storing prefetched data for a misaligned memory access.
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Goodhue, Gregory K.; Khan, Ata R.; Wharton, John H., Cyclically sequential memory prefetch.
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Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions.
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Sawyers, Thomas P., Look-ahead processor for signaling suitable non-idle performance state for main processor.
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Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Mechanism for high performance transfer of speculative request data between levels of cache hierarchy.
상세보기
Goodhue, Gregory K; Khan, Ata R; Wharton, John H.; Kallal, Robert Michael, Memory accelerator for ARM processor pre-fetching multiple instructions from cyclically sequential memory partitions.
상세보기
Goodhue,Gregory K.; Khan,Ata R.; Wharton,John H.; Kallal,Robert Michael, Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio.
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Minami, Toshiaki, Memory control apparatus and method.
상세보기
Chiba Takashi (Kawasaki JPX), Memory control system using a single access request for doubleword data transfers from both odd and even memory banks.
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Sachs Howard G. (Los Gatos CA) Cho James Y. (Los Gatos CA) Hollingsworth Walter H. (Campbell CA), Method and apparatus for addressing a cache memory.
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Dahl Stephen A. ; Endicott John C. ; Heyrman Peter J. ; Kirkman R. Karl ; Mustain Richard G. ; Peterson Jon H., Method and data processing system for emulating a program.
상세보기
Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Method for instruction extensions for a tightly coupled speculative request unit.
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Tsubota, Masashi, Micro-processor.
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Kusakabe Hiroyuki (Tokyo JPX), Programmable controller with timing control.
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Liu Lishing (Pleasantville NY), Sequential prefetching with deconfirmation.
상세보기
Samuels Michael W. (San Jose CA) Zasio John J. (Sunnyvale CA), Simulation system.
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Smith, David W., System and method for controlling bus access for bus agents having varying priorities.
상세보기
Mes,Ian, System and method for reducing access latency to shared program memory.
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Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Time based mechanism for cached speculative data deallocation.
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Data Processor system having look-ahead control 원문보기

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연합인증

Data Processor system having look-ahead control 원문보기

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