$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색도움말
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

통합검색

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

Surface mounted array strain relief device

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H05K-001/18   
미국특허분류(USC) 361/408 ; 174/52FP ; 361/421 ; 439/81
출원번호 US-0934297 (1986-11-24)
발명자 / 주소
  • Simpson John P. (Apalachin NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 54  인용 특허 : 0
초록

An electrical assembly having an integrated circuit package which has a plurality of electrical conductors fixed thereto. The electrical conductors form mechanical and electrical connections. Each of the electrical conductors has a root at one end and a tip at the other end. The root of each conductor is attached to the integrated circuit package to form a fixed electrical and mechanical connection. The tip of each conductor is adapted to be connected to a surface at a predetermined location. Each of the electrical conductors has at least two bends betwe...

대표
청구항

An electrical assembly comprising: (a) a printed circuit board having at least one major surface having predetermined locations thereon which are adapted to receive electrical conductors; (b) a substantially planar integrated circuit package having a plurality of electrical conductors fixed thereto and extending therefrom so as to form mechanical and electrical connections between said printed circuit board and said integrated circuit package, said integrated circuit package having a central area and a periphery surrounding said central area, some of sai...

이 특허를 인용한 특허 (54)

  1. Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.
  2. Fjelstad Joseph, Compliant wirebond packages having wire loop.
  3. Gunsei Kimoto JP, Contact and contact assembly using the same.
  4. Khandros,Igor Y., Contact structures and methods for making same.
  5. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING.
  6. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y; Mathieu, Gaetan L., ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING.
  7. Barlow Alan (Cheltenham GB2), Electrical components and assemblies.
  8. Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic component with terminals and spring contact elements extending from areas which are remote from the terminals.
  9. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  10. Goldmann, Lewis S.; Prasad, Chandrika, Full wafer test configuration using memory metals.
  11. Kman Stephen Joseph ; Stubecki John Arthur ; Sondej William Richard, Hammer for forming bulges in an array of compliant pin blanks.
  12. VanHouten, Dennis J.; Kring, Christopher S.; Sapak, Ben; Johnson, Jack L., Headliner with integral wire harness.
  13. Donner Edward O. (Poughkeepsie NY) Zumbrunnen Michael L. (Rochester MN), High density and high current capacity pad-to-pad connector comprising of spring connector elements (SCE).
  14. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  15. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Interposer, socket and assembly for socketing an electronic component and method of making and using same.
  16. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method and apparatus for burning-in semiconductor devices in wafer form.
  17. Khandros Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  18. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  19. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  20. Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu, Method of fabricating an interconnection element.
  21. Busacco Raymond A. (Lake Ariel PA) Chapin Fletcher W. (Vestal NY) Dranchak David W. (Endwell NY) Molla Jaynal A. (Endicott NY) Saxenmeyer ; Jr. George J. (Apalachin NY) Topa Robert D. (Binghamton NY), Method of forming a conductive end portion on a flexible circuit member.
  22. Kman Stephen Joseph ; Stubecki John Arthur ; Sondej William Richard, Method of forming a pinned module.
  23. Fjelstad, Joseph; Smith, John W.; DiStefano, Thomas H.; Zaccardi, James; Walton, A. Christian, Method of making an electronic contact.
  24. Khandros Igor Y., Method of mounting free-standing resilient electrical contact structures to electronic components.
  25. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.
  26. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out.
  27. Distefano Thomas H. ; Smith ; Jr. John W., Methods of making connections to a microelectronic unit.
  28. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Methods of removably mounting electronic components to a circuit board, and sockets formed by the methods.
  29. Fjelstad, Joseph; Beroz, Masud; Smith, John W.; Haba, Belgacem, Microelectric packages having deformed bonded leads and methods therefor.
  30. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  31. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  32. Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Mounting spring elements on semiconductor devices, and wafer-level testing methodology.
  33. John W. Smith ; Belgacem Haba, Multi-layer substrates and fabrication processes.
  34. Smith, John W.; Haba, Belgacem, Multi-layer substrates and fabrication processes.
  35. Brodsky, William Louis; Chan, Benson; Gaynes, Michael Anthony; Markovich, Voya Rista, Printed wiring board interposer sub-assembly.
  36. Khandros, Jr., Igor Y.; Sporck, Jr., A. Nicholas; Eldridge, Jr., Benjamin N., Probe card assembly.
  37. Khandros,Igor Y.; Sporck,A. Nicholas; Eldridge,Benjamin N., Probe card assembly.
  38. Eldridge, Benjamin N.; Khandros, Igor Y.; Sporck, A. Nicholas, Probe card assembly and kit.
  39. Khandros,Igor Y.; Sporck,A. Nicholas; Eldridge,Benjamin N., Probe card assembly and kit.
  40. Khandros,Igor Y.; Sporck,A. Nicholas; Eldridge,Benjamin N., Probe card assembly and kit.
  41. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  42. Khandros,Igor Y.; Mathieu,Gaetan L., Probe for semiconductor devices.
  43. Khandros,Igor Y.; Mathieu,Gaetan L., Probe for semiconductor devices.
  44. Donner Edward O. (Poughkeepsie NY) Zumbrunnen Michael L. (Rochester MN), Process for manufacture of spring contact elements and assembly thereof.
  45. Fjelstad Joseph, Process of manufacturing compliant wirebond packages.
  46. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Resilient contact structures for interconnecting electronic devices.
  47. Eldridge,Benjamin Niles; Grube,Gary William; Khandros,Igor Yan; Mathieu,Gaetan L., Resilient contact structures formed and then attached to a substrate.
  48. Khandros Igor Y. ; Mathieu Gaetar L., Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components.
  49. Ideta Yasushi,JPX ; Washitani Akihiro,JPX ; Umetsu Tsunenori,JPX ; Kaneko Keiko,JPX ; Kobayashi Kunio,JPX, Semiconductor device socket.
  50. Khandros Igor Y. ; Mathieu Gaetar L., Semiconductor devices with integral contact structures.
  51. DiStefano,Thomas H.; Smith,John W.; Faraci,Tony, Semiconductor package with heat sink.
  52. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  53. Palmer Edward R.,GBX ; Stratford Colin,GBX, Surface mount electronic reed switch component with transverse lead wire loops.
  54. VanHouten, Dennis J.; Kring, Christopher S.; Sapak, Ben; Johnson, Jack L., Vehicle interior panel with integral wire harness.