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Etching method for producing an electrochemical cell in a crystalline substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/306
  • B44C-001/22
  • C03C-015/00
  • C23F-001/02
출원번호 US-0073739 (1987-07-15)
발명자 / 주소
  • Holland Christopher E. (Redwood City CA) Westerberg Eugene R. (Palo Alto CA) Madou Marc J. (Palo Alto CA) Otagawa Takaaki (Fremont CA)
출원인 / 주소
  • SRI International (Menlo Park CA 02)
인용정보 피인용 횟수 : 61  인용 특허 : 0

초록

A method is set forth of constructing an electrochemical cell from a crystalline slab having front and back sides facing generally away from one another. Masking layers are provided covering the front and back sides of the slab and a back resist layer is provided covering the front masking layer, th

대표청구항

A method of constructing an electrochemical cell in a crystalline slab having front and back sides facing generally away from one another, comprising: (a) providing first front and first back masking layers of a first thickness covering, respectively, said front and back sides and a front resist lay

이 특허를 인용한 특허 (61)

  1. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  2. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  3. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  4. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  5. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  6. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  7. Haba, Belgacem, Conductive pads defined by embedded traces.
  8. Haba, Belgacem, Conductive pads defined by embedded traces.
  9. Sickafus Edward N. (Grosse Ile MI) Mikkor Mati (Ann Arbor MI), Directional aperture etched in silicon.
  10. Madou, Marc J.; Daunert, Sylvia, Dual stage microvalve and method of use.
  11. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  12. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  13. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  14. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  15. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  16. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking with leads extending along edges.
  17. Crumly, William F.; Madou, Marc J., Electrochemical microsensor package.
  18. Shiv, Lior, Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane.
  19. Shiv, Lior, Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane.
  20. Shiv, Lior, Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane.
  21. Haba, Belgacem; Mohammed, Ilyas, Method of fabricating stacked assembly including plurality of stacked microelectronic elements.
  22. Haba, Belgacem, Method of fabricating stacked packages with bridging traces.
  23. Gaul Stephen J. (Melbourne FL), Method of fabrication of surface mountable integrated circuits.
  24. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  25. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  26. Oganesian, Vage; Haba, Belgacem; Mitchell, Craig; Mohammed, Ilyas; Savalia, Piyush, Methods of forming semiconductor elements using micro-abrasive particle stream.
  27. Fix, Richard; Kunz, Denis; Krauss, Andreas; Sahner, Kathy; Nolte, Philipp, Microelectrochemical sensor and method for operating a microelectrochemical sensor.
  28. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Microelectronic elements having metallic pads overlying vias.
  29. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Microelectronic elements with rear contacts connected with via first or via middle structures.
  30. Zhao, Mingqi; Vanysek, Petr; Ricco, Antonio; Lackritz, Hilary S.; Qun, Zhu; Nguyen, Uyen; Bjornson, Torleif O., Microfluidic chip having integrated electrodes.
  31. Madou, Marc J., Microfluidic devices and manufacture thereof.
  32. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  33. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  34. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  35. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip VIAS in stacked chips.
  36. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura, Off-chip vias in stacked chips.
  37. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  38. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  39. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Haba, Belgacem; Oganesian, Vage, Packaged semiconductor chips.
  40. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  41. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  42. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  43. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura, Reconstituted wafer stack packaging with after-applied pad extensions.
  44. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura Wills, Reconstituted wafer stack packaging with after-applied pad extensions.
  45. Haba, Belgacem; Humpston, Giles; Margalit, Moti, Semiconductor packaging process using through silicon vias.
  46. Haba, Belgacem; Humpston, Giles; Margalit, Moti, Semiconductor packaging process using through silicon vias.
  47. Avsian, Osher; Grinman, Andrey; Humpston, Giles; Margalit, Moti, Stack packages using reconstituted wafers.
  48. Haba, Belgacem; Mohammed, Ilyas, Stacked assembly including plurality of stacked microelectronic elements.
  49. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.
  50. Haba, Belgacem; Oganesian, Vage; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Stacked microelectronic assembly having interposer connecting active chips.
  51. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  52. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  53. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages with plural active chips.
  54. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  55. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  56. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assemby with TSVS formed in stages and carrier above chip.
  57. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  58. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  59. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  60. Braymen Steven D. (Ames IA) Paulson Bradley A. (Ames IA) Goedken Kenneth D. (Dubuque IA), Use of sol-gel derived tantalum oxide as a protective coating for etching silicon.
  61. Haba, Belgacem; Mohammed, Ilyas; Mirkarimi, Laura; Kriman, Moshe, Wafer level edge stacking.
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