초록 ▼

A video transceiver includes a compressor which grabs a pair of blocks of image data from a video frame store and loads them into a dual port memory. A first processor, working through one of the dual ports, performs a portion of an image compression algorithm, while a second processor, working thro

A video transceiver includes a compressor which grabs a pair of blocks of image data from a video frame store and loads them into a dual port memory. A first processor, working through one of the dual ports, performs a portion of an image compression algorithm, while a second processor, working through a second one of the dual ports, performs the remainder of the compression algorithm on each one of the two pairs of blocks, both processors operating in parallel to speed up the entire process. A key word in each block is changed in accordance with each step, so that each of the two processors is prevented from grabbing the wrong one of the two blocks from the dual port memory. The resulting compressed data is queued in a temporary buffer, from which it is returned to another portion of the video frame store in serial fashion, rather than block, in preparation for serial transmission.

대표청구항 ▼

A still video transceiver, comprising: a digital video frame store memory adaptable to store plural blocks of video data; a dual port memory having first and second memory ports; means for fetching dual blocks of video data from said frame store memory and for loading said dual blocks into said dual

A still video transceiver, comprising: a digital video frame store memory adaptable to store plural blocks of video data; a dual port memory having first and second memory ports; means for fetching dual blocks of video data from said frame store memory and for loading said dual blocks into said dual port memory; digital signal processor means for accessing through said first memory port and discrete cosine transforming each one of said dual blocks to generate a corresponding block of transform coefficients; data processing means for accessing through said second port and compressing each block of said transform coefficients to generate a batch of compressed transform coefficients therefrom, whereby said digital signal processing means and said data processing means may operate virtually simultaneously upon different respective ones of said dual blocks.