초록 ▼

Configured for accelerated operation of processing elements in a SIMD parallel processing system is disclosed. The output of an exclusive-OR gate is coupled to one input of the element ALU while a first input of the gate is adapted to receive signals intended for the ALU input. Upon loading a ‘1’bit

Configured for accelerated operation of processing elements in a SIMD parallel processing system is disclosed. The output of an exclusive-OR gate is coupled to one input of the element ALU while a first input of the gate is adapted to receive signals intended for the ALU input. Upon loading a ‘1’bit into a register coupled to a gate second input, signals applied to the gate first input are complemented and applied to the ALU input. As a result, different arithmetic and logic operations can be performed simultaneously by different elements in the processing system in response to a single series of instructions.

대표청구항 ▼

A processing element for use in a single instruction multiple data parallel processing system comprising a plurality of said processing elements, said element comprising: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto;

A processing element for use in a single instruction multiple data parallel processing system comprising a plurality of said processing elements, said element comprising: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to said ALU; memory means for storing a signal, the signal stored in said memory means being outputted to said gate; and said gate providing said output signal to said ALU as the complement of said first input signal only upon a second being stored in said memory means and thereby outputted to said gate, said gate providing said output signal to said ALU as said first input signal in the absence of said second signal; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the non-selected elements perform the instructed operation on said first input signal.