초록 ▼

An integrated circuit sensor circuit (10) is disclosed which is operable in differential or single-ended modes at DC input potentials which can be below the integrated circuit substrate bias potential (ground). Substrate injection is prevented and the circuit is operable for input signals which can

An integrated circuit sensor circuit (10) is disclosed which is operable in differential or single-ended modes at DC input potentials which can be below the integrated circuit substrate bias potential (ground). Substrate injection is prevented and the circuit is operable for input signals which can vary relatively widely with respect to the substrate bias potential. This is accomplished even though only a single polarity power supply (+5 volts) with respect to substrate bias potential is used for the integrated circuit. An input stage of an integrated circuit (16) comprises a pair of identical polarity transistors (23, 24) operated in a differential common base mode with an opposite polarity transistor (25) used to supply appropriate bias potential to the common base connection. This prevents substrate injection while maintaining a wide operative range for the sensor circuit. Additional substrate injection preventing circuitry (31) is provided to maintain the collectors of the differential input transistors above the integrated circuit substrate base potential, and input protection circuitry (32-35) is used to limit the magnitude of applied input signals.

대표청구항 ▼

A sensor circuit comprising: an integrated circuit (IC) having a substrate base with a predetermined bias voltage applied thereto; said integrated circuit including first and second identical polarity transistors each having base, emitter and collector electrodes, said base electrodes being DC conne

A sensor circuit comprising: an integrated circuit (IC) having a substrate base with a predetermined bias voltage applied thereto; said integrated circuit including first and second identical polarity transistors each having base, emitter and collector electrodes, said base electrodes being DC connected together and first and second input signal terminals of said integrated circuit coupled, respectively, to the emitter electrodes of said first and second transistors; said IC including an opposite polarity third transistor with base, emitter and collector electrodes and having its base and collector electrodes connected between an integrated circuit terminal having a reference voltage provided thereat and said commonly connected base electrodes of said first and second transistors, and an output terminal provided at the collector electrode of said second transistor, wherein said second transistor provides an output signal at said output terminal which is determined by at least the input signal provided at said first input terminal, whereby input bias voltages substantially below the predetermined bias voltage applied to said IC substrate base can be tolerated while said integrated circuit provides said output signal at said output terminal; wherein said integrated circuit includes additional collector voltage protection circuitry means coupled to the collector electrodes of said first and second transistors for preventing the voltage at said collector electrodes from exceeding a predetermined voltage level with respect to said integrated circuit substrate bias potential despite the voltage applied to said input terminals, whereby forward biasing the integrated circuit substrate base isolation junction is prevented.