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Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic bl 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
  • G06F-009/44
  • G06I-012/02
  • G06I-012/08
출원번호 US-0809989 (1985-12-17)
발명자 / 주소
  • Munshi Ashfaq A. (San Jose CA) Schimpf Karl M. (Santa Cruz CA)
출원인 / 주소
  • International Business Machine Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 65  인용 특허 : 10

초록

A method for allocating and optimizing register assignments during compiling of source into executable code in either a scalar or vector processor uses a pebble game heuristic played on each basic block dependency graph for local optimization. Like variable analysis and loop unrolling are used for g

대표청구항

A method for allocating and optimizing register assignments during the compiling of source into executable code in either a scalar or a vector processor, the source code including regions of code without branches termed “basic blocks”, each basic block having statements defining computations, each p

이 특허에 인용된 특허 (10)

  1. Gates Dirk I. (Chatsworth CA) Rosen David B. (Canoga Park CA) Jones Gary A. (Chatsworth CA), Compiler for evaluating Boolean expressions.
  2. Goss Clinton (New York NY) Rosenberg Richard (Brooklyn NY) Whyte Peter (Fort Lee NJ), Compilers using a universal intermediate language.
  3. Chaitin Gregory J. (Yorktown Heights NY) Hopkins Martin E. (Chappaqua NY) Markstein Peter W. (Yorktown Heights NY) Warren ; Jr. Henry S. (Ossining NY), Generating storage reference instructions in an optimizing compiler.
  4. Auslander Marc A. (Millwood NY) Cocke John (Bedford NY) Markstein Peter W. (Yorktown Heights NY), Method for improving global common subexpression elimination and code motion in an optimizing compiler.
  5. Kim Dongsung R. (Laguna Hills CA) McClintock ; Jr. John H. (Mission Viejo CA), Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation.
  6. Saad Henry Y. (San Jose CA) Tindall William N. J. (San Martin CA), Optimizing cobol object code instruction path length with respect to perform statements.
  7. Chaitin Gregory J. (Yorktown Heights NY), Register allocation and spilling via graph coloring.
  8. Kim, Dongsung R., Register allocation apparatus.
  9. Rizzi John R. (San Jose CA), Register allocation system using recursive queuing during source code compilation.
  10. Masui Shoichi (Kawasaki JPX) Tano Shunichi (Machida JPX) Funabashi Motohisa (Sagamihara JPX) Haruna Koichi (Yokohama JPX), Resource allocation method in a computer system.

이 특허를 인용한 특허 (65)

  1. Blandy, Geoffrey Owen, Apparatus and method for an enhanced integer divide in an IA64 architecture.
  2. Blandy, Geoffrey Owen; Johnson, Andrew, Apparatus and method for avoiding deadlocks in a multithreaded environment.
  3. Blandy, Geoffrey Owen, Apparatus and method for creating instruction bundles in an explicitly parallel architecture.
  4. Blandy, Geoffrey Owen; Johnson, Andrew; Shi, Danling, Apparatus and method for creating instruction groups for explicity parallel architectures.
  5. Blandy, Geoffrey Owen, Apparatus and method for detecting and handling exceptions.
  6. Babaian Boris A.,RUX ; Gorokhov Valeri G.,RUX ; Gruzdov Feodor A.,RUX ; Sakhin Yuli Kh.,RUX ; Volkonski Vladimir Yu.,RUX, Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor.
  7. Koseki,Akira; Komatsu,Hideaki, Compiler and register allocation method.
  8. Podanoffsky, Michael, Computerized database system and method.
  9. Aizikowitz Nava E.,ILX ; Bar-Haim Roy N.,ILX ; Edelstein Orit,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph, Cooperation of global and local register allocators for better handling of procedures.
  10. Brown, David W.; Clark, Jay S., Data routing systems and methods.
  11. Brown, David W.; Clark, Jay S., Database event driven motion systems.
  12. Clewis,Fred T.; Sitze,Richard A., Directed non-cyclic graph walking system for data processing and analysis in software application.
  13. Bishop John, Enabling troubleshooting of subroutines with greatest execution time/input data set size relationship.
  14. Czajkowski, Grzegorz J., Estimating a dominant resource used by a computer program.
  15. Brown,David W.; Clark,Jay S., Event driven motion systems.
  16. Brown,David W.; Stein,Skylar, Event management systems and methods for the distribution of motion control commands.
  17. Verbitsky,George, Expanding a software program by insertion of statements.
  18. Goebel Kurt J., Float register spill cache method, system, and computer program product.
  19. Goebel Kurt J., Functional unit switching for the allocation of registers.
  20. Brown, David W.; Clark, Jay S., Generation and distribution of motion commands over a distributed network.
  21. Ju Dz-ching ; Gillies David M., Global control flow treatment of predicated code.
  22. Garvey,Joseph F.; Jeffries,Clark D., Global processor resource assignment in an assembler.
  23. Ostanevich, Alexander Y., Hardware supported software pipelined loop prologue optimization.
  24. Kushlis,Robert J, Inter-procedure global register allocation method.
  25. Srivastava Amitabh, Link time optimization with translation to intermediate program and following optimization techniques including program.
  26. Archambault, Roch Georges; Blainey, Robert James, Loop allocation for optimizing compilers.
  27. Grove Daniel D. (Mountain View CA) Schwartz David C. (San Antonio TX), Method and apparatus for an improved optimizing compiler.
  28. Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interprocedural register allocation.
  29. Biggerstaff Ted J., Method and system for anticipatory optimization of computer programs.
  30. Gillet Marc J. L. (Redwood City CA), Method and system for eliminating operation codes from intermediate prolog instructions.
  31. Simonyi, Charles, Method and system for generating a computer program.
  32. Simonyi Charles, Method and system for generating and displaying a computer program.
  33. Simonyi Charles, Method and system for reducing an intentional program tree represented by high-level computational constructs.
  34. Simonyi Charles, Method and system for reducing an intentional program tree represented by high-level computational constructs.
  35. Simonyi Charles, Method and system for reducing an intentional program tree represented by high-level computational constructs.
  36. Simonyi Charles, Method and system for reducing an intentional program tree represented by high-level computational constructs.
  37. Simonyi Charles, Method and system for reducing an intentional program tree represented by high-level computational constructs.
  38. Goebel Kurt J., Method and system for register allocation using multiple interference graphs.
  39. Goebel Kurt J., Method and system for wrapper routine optimization.
  40. Radigan Jim J., Method for determining the set of variables that may be ambiguously defined at a point in a computer program.
  41. Radigan Jim J., Method for identifying partial redundancies in a new processor architecture.
  42. Radigan Jim J., Method for identifying partial redundancies in existing processor architectures.
  43. Kim Young-No,KRX, Method for minimizing the number of input terminals used in an operator.
  44. Radigan Jim J., Method for optimizing a loop in a computer program by speculatively removing loads from within the loop.
  45. Liu Kin-Yip ; Shoemaker Ken ; Hammond Gary ; Pai Anand ; Yellamilli Krishna, Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor.
  46. Radigan Jim J., Method for using static single assignment to color out artificial register dependencies.
  47. Jansson Rickard (Stockholm SEX), Method of avoiding non-desired interference between services by creating a truncated binomial tree which represent activ.
  48. Brown, David W.; Clark, Jay S., Motion control systems.
  49. Brown,David W., Motion control systems and methods.
  50. Brown,David W., Motion control systems and methods.
  51. Ngo Viet N. ; Tsai Wei-Tek, Outer loop vectorization.
  52. Udayakumaran, Sumesh, Register allocation for graphics processing.
  53. Chen, Wei-Yu; Lueh, Guei-Yuan, Register allocation for message sends in graphics processing pipelines.
  54. Aizikowitz Nava Arela,ILX ; Asnash Liviu,ILX ; Bar-Haim Roy,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph ; Schmidt William Jon, Register allocation method and apparatus for gernerating spill code as a function of register pressure compared to dual.
  55. Aizikowitz Nava Arela,ILX ; Bar-Haim Roy,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph ; Schmidt William Jon, Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system.
  56. Goebel Kurt J., Register allocation via selective spilling.
  57. Goebel Kurt, Register resource allocation feedback.
  58. Brown, Stephen J.; Brown, David W., Remote generation and distribution of command programs for programmable devices.
  59. Tanaka Akira,JPX ; Sayama Junko,JPX ; Yukawa Hiroshi,JPX ; Odani Kensuke,JPX, Resource assigning apparatus which assigns the variable in a program to resources.
  60. Sarkar Vivek ; Serrano Mauricio Jose ; Simons Barbara Bluestein, Retargeting optimized code by matching tree patterns in directed acyclic graphs.
  61. Thompson,Carol L.; Littfin,Jeff, Specifying an invariant property (range of addresses) in the annotation in source code of the computer program.
  62. Goebel Kurt J., System and method for reducing the occurrence of window use overflow.
  63. Brown,David W.; Clark,Jay S., System and methods for generating and communicating motion data through a distributed network.
  64. MacLeod Andrew Wilfred,CAX, System for local context spilling for graph coloring register allocators.
  65. Verbitsky,George, Use of different color sequences for variables of different sizes and different semantics.
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