초록 ▼

Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device arbitration are provided for, and the modes may be mixed among devices, and changed during operation of the syste

Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device arbitration are provided for, and the modes may be mixed among devices, and changed during operation of the system, in the system without interfering with communications. The arbitration mechanism requires only a single additional line in the communications pathway, and thus a single additional pin on the integrated circuit on which it is implemented, for the arbitration function. It thus facilitates implementation of the arbitration mechanism along with all other interconnect logic on a single integrated circuit.

대표청구항 ▼

An interconnecting circuit in a device for providing a communications interface for that device to a non-pended bus, wherein the device has a unique ID number and initiates a transaction at times when a request signal is asserted by asserting a busy line to obtain access to the bus, the bus includin

An interconnecting circuit in a device for providing a communications interface for that device to a non-pended bus, wherein the device has a unique ID number and initiates a transaction at times when a request signal is asserted by asserting a busy line to obtain access to the bus, the bus including a plurality of information lines, a plurality of data lines, a no arbitration line, and the busy line, and wherein each of the transactions has a command/address cycle followed by an imbedded arbitration cycle which is then followed by at least one data cycle, the circuit comprising: controller means coupled to the no arbitration and busy lines and responsive to a de-assertion of the no arbitration line for indicating when the imbedded arbitration cycle is occurring; driver means coupled to the controller means for asserting one of two data lines corresponding to the device during the imbedded arbitration cycle; priority resolution means coupled to the data lines for asserting a won arbitration signal to indicate that the device had the highest priority during the imbedded arbitration cycle, wherein assertion of the won arbitration signal enables the device to assert the busy line during a subsequent cycle after said busy line is de-asserted by a previous device having access to the bus during the current transaction; receive register means coupled to the information lines for comparing the ID number of the device with an ID number of the previous device which is present of the information lines during the imbedded arbitration cycle, and for setting an indicator in either a first or second state according to whether the ID number of the device seeking to initiate a transaction is greater than that of the previous device; and switching means, responsive to the receive register means and coupled to the driver means, for asserting a low priority data line corresponding to the device during the imbedded arbitration cycle of the next transaction when the indicator is in the first state, and for asserting a high priority data line corresponding to the device during the imbedded arbitration cycle of the next transaction when the indicator is in the second state, wherein the device has a variable priority and is allocated access to the bus fairly according to a dual-count, dual round robin algorithm.