초록 ▼

The invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a me

The invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a memory dedicated to the host microprocessor. For example, the cache memory can be reconfigured from a 2K byte by 16-bit space during the acquisition mode to a 4K byte ×8-bit space during the retrieval mode, wherein the high and low bytes of the previously defined 16-bit words are interleaved.

대표청구항 ▼

An apparatus for interfacing between a peripheral device which outputs Q-bit data words and a host processor having an N bit data bus, wherein data are acquired from the peripheral device during an acquisition mode and retrieved from said interface apparatus during a retrieval mode, said apparatus c

An apparatus for interfacing between a peripheral device which outputs Q-bit data words and a host processor having an N bit data bus, wherein data are acquired from the peripheral device during an acquisition mode and retrieved from said interface apparatus during a retrieval mode, said apparatus comprising: a plurality of single port memories, each memory having a M byte by N bit memory space; a first bus transceiver means for connecting, during the acquisition mode, a different N bit portion of said Q bit data word to each of said plurality of memories; a second bus transceiver means for directly connecting, during the retrieval mode, the data lines of each of said plurality of memories to the host processor N bit data bus; a counter means for generating an incremental address each time the peripheral generates a new data word; an address multiplexing means, for connecting the address lines of each of said plurality of single port memories to said counter means during the acquisition mode, and for directly connecting the address lines of each of said plurality of single port memories to certain most significant bits of he host processor address bus during the retrieval mode; and, a selector means, operably connected to each of said plurality of single port memories, for alternatively enabling each of said plurality of single port memories in response to certain least significant bits of the host processors address bus during the retrieval mode.