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Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided o 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/283
출원번호 US-0001067 (1987-01-07)
우선권정보 NL-0000021 (1986-01-08)
발명자 / 주소
  • Peters Johannes S. (Nijmegen NLX)
출원인 / 주소
  • U.S. Philips Corporation (New York NY 02)
인용정보 피인용 횟수 : 52  인용 특허 : 9

초록

A method of manufacturing a semiconductor device comprising a semiconductor body (1), of which a surface (13) is provided with a metallization (15,16,17,18) with a thick connection electrode (19). The metallization is formed in a first metal layer (49) and the connection electrode is formed in a sec

대표청구항

A method of manufacturing a semiconductor device comprising the steps of forming a semiconductor body having respective transistor zones, forming an insulating layer on said semiconductor body, said insulating layer having openings to at least some of said transistor zones, successively forming at l

이 특허에 인용된 특허 (9)

  1. Dalal Hormazdyzr D. (Wappingers Falls NY) Patnaik Bisweswar (Wappingers Falls NY) Sarkary Homi G. (Hopewell Junction NY), Forming interconnections for multilevel interconnection metallurgy systems.
  2. Robinson John Thomas (Dallas TX) Edwards Richard A. (Richardson TX), Gold-germanium alloy contacts for a semiconductor device.
  3. Harris James M. (San Jose CA), Method for forming gang bonding bumps on integrated circuit semiconductor devices.
  4. Karulkar Pramod C. (Diamond Bar CA), Method for making a reliable ohmic contact between two layers of integrated circuit metallizations.
  5. Fontana ; Jr. Robert E. (Dallas TX) Bullock David C. (Dallas TX) Singh Shalendra K. (Dallas TX) Bush John M. (Plano TX), Method of fabricating magnetic bubble memory device having planar overlay pattern of magnetically soft material.
  6. Shibata Hiroshi (Kanagawa JPX), Pattern forming method.
  7. Flowers Dervin L. (Scottsdale AZ) Greeson Richard L. (Scottsdale AZ) Rice V. Louise (Phoenix AZ), Semiconductor device having a tin metallization system and package containing same.
  8. Owyang King (Baldwinsville NY) Stein ; deceased Leonard (late of Dewitt NY by Vera Stein ; executrix), Semiconductor device with built-up low resistance contact.
  9. Hall Ronald D. (Baltimore MD), Thin film microstrip circuits.

이 특허를 인용한 특허 (52)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  5. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  8. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  9. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  10. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  11. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  12. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  19. Roane Bobby A. (Manvel TX), Method and apparatus for providing interconnection between metallization layers on semiconductors devices.
  20. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  21. Den Blanken Hubertus J. (Eindhoven NLX), Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and abo.
  22. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  23. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  35. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  36. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  37. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  40. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  52. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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