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Temperature compensation circuit for a delay circuit utilized in an FM detector 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-007/14
  • G11B-007/00
출원번호 US-0030159 (1987-03-25)
우선권정보 JP-0047499 (1986-03-31)
발명자 / 주소
  • Fujishima Masakazu (Hamamatsu JPX)
출원인 / 주소
  • Nippon Gakki Seizo Kabushiki Kaisha (Hamamatsu JPX 03)
인용정보 피인용 횟수 : 51  인용 특허 : 2

초록

A circuit for compensating change in delay time of a delay circuit due to variation in temperature employs, as a phase shifter of a pulse FM detection circuit, a delay circuit whose delay time is subject to change due to variation in temperature and can be controlled in response to a control signal.

대표청구항

A temperature compensation circuit for a delay circuit comprising: a delay circuit which is used as a phase-shifter in a pulse FM detection circuit and whose delay time changes depending upon temperature and can be controlled in response to a control signal; a dc component detection circuit for dete

이 특허에 인용된 특허 (2)

  1. Doyle James T. (Tucson AZ), CMOS input level shifting circuit with temperature-compensating n-channel field effect transistor structure.
  2. Moberg Gregory O. (Rochester NY), fm Demodulator with temperature compensation.

이 특허를 인용한 특허 (51)

  1. Wasson Timothy M., Delay stabilization system for an integrated circuit.
  2. Ward, Christopher M.; Vorenkamp, Pieter, Differential crystal oscillator.
  3. Woo,Agnes Neves; Chen,Chun Ying, ESD configuration for low parasitic capacitance I/O.
  4. Woo, Agnes Neves, ESD protection for high voltage applications.
  5. Woo,Agnes Neves, ESD protection for high voltage applications.
  6. Wu, Mao-Lin; Shen, Chih-Hung; Ho, Yu-Ping, Electronic system capable of compensating process, voltage and temperature effects.
  7. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank; Ward, Christopher M.; Duncan, Ralph; Kwan, Tom W.; Chang, James Y. C.; Khorramabadi, Haideh, Fully integrated tuner architecture.
  8. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank; Ward, Christopher M.; Duncan, Ralph; Kwan, Tom W.; Chang, James Y. C.; Khorramabadi, Haideh, Fully integrated tuner architecture.
  9. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank; Ward,Christopher M.; Duncan,Ralph; Kwan,Tom W.; Chang,James Y. C.; Khorramabadi,Haideh, Fully integrated tuner architecture.
  10. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank; Ward,Christopher M.; Duncan,Ralph; Kwan,Tom W.; Chang,James Y. C.; Khorramabadi,Haideh, Fully integrated tuner architecture.
  11. Duncan, Ralph; Kwan, Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
  12. Duncan,Ralph; Kwan,Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
  13. Chang, James Y. C., Integrated spiral inductor.
  14. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  15. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  16. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  17. Bult,Klaas; Gomez,Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  18. Le, Huy; Kopley, Thomas Edward, Integrator/ comparator control of ring oscillator frequency and duty cycle.
  19. Tomisawa Norio (Hamamatsu JPX), Jitter control circuit having signal delay device using CMOS supply voltage control.
  20. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
  21. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
  22. Behzad,Arya R., Large gain range, high linearity, low noise MOS VGA.
  23. Austin H. Lesea, Method and apparatus for adjusting delay in a delay locked loop for temperature variations.
  24. Chang, James Y. C., Multi-track integrated circuit inductor.
  25. Chang, James Y. C., Multi-track integrated spiral inductor.
  26. Ward, Christopher M.; Vorenkamp, Pieter, Phase locked loop.
  27. Exeter, George Ronald, Ring topology based voltage controlled oscillator.
  28. Agnes N. Woo ; Kenneth R. Kindsfater ; Fang Lu, System and method for ESD Protection.
  29. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  30. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  31. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  32. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  33. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  34. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
  35. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
  36. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for coarse/fine PLL adjustment.
  37. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank, System and method for coarse/fine PLL adjustment.
  38. Khorramabadi, Haideh, System and method for linearizing a CMOS differential pair.
  39. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
  40. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
  41. Ralph Duncan ; Tom W. Kwan, System and method for narrow band PLL tuning.
  42. Vorenkamp Pieter ; Bult Klaas,NLX ; Carr Frank, System and method for on-chip filter tuning.
  43. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  44. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  45. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  46. Carr,Frank; Vorenkamp,Pieter, System and method for providing a low power receiver design.
  47. Frank Carr ; Pieter Vorenkamp, System and method for providing a low power receiver design.
  48. Gillette Garry C., System for compensating for temperature induced delay variation in an integrated circuit.
  49. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, Temperature compensation for internal inductor resistance.
  50. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, Temperature compensation for internal inductor resistance.
  51. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank, Temperature compensation for internal inductor resistance.
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