초록 ▼

A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general system memory 5, or so as to constitute instructi

A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general system memory 5, or so as to constitute instructions for a video processor 2. In this latter case, the address controls an operation cycle of a first priority for controlling the processor or executes a series of operations with a lower priority, such lower priority operations allowing processor 2 to process image information without the intervention of the central unit. The invention finds application in such areas as teletext systems and video games.

대표청구항 ▼

A system for displaying graphic information on a video screen, comprising: memory means having a plurality of addressable memory locations in which said graphic information is to be stored; a central processing unit for controlling the information to be displayed; video display processor means for p

A system for displaying graphic information on a video screen, comprising: memory means having a plurality of addressable memory locations in which said graphic information is to be stored; a central processing unit for controlling the information to be displayed; video display processor means for producing said graphic information and for storing said graphic information in said memory means; communication bus means interconnecting said memory means, said central processing unit, and said video display processor means, said central processing unit presenting information on said communication bus means as time-multiplexed address and data fields, said address field defining an address space having first and second value ranges, said first value range of the address space defined by said address field corresponding to locations in said memory means addressable by said central processing unit, said second value range of the address space defined by said address field corresponding to a set of instructions for the video display processor means; said video display processor means being connected to said memory means for accessing and modifying the contents of locations in said memory means containing said graphic information; control circuit means connected to said central processing unit, said video display processor means and said memory means for controlling access to said memory means by said video display processor means and said central processing unit; interpretation means connected to said communication bus means, said control circuit means and said video display processor means for decoding the address fields presented by said central processing unit on said communication bus means; said control circuit means being responsive to receiving a decoded address value in said first value range of said address space defined by said address field for enabling access between said central processing unit and said memory means, and being responsive to receiving a decoded address value in said second value range of said address space defined by said address field for controlling said video display processor means to execute an instruction corresponding to the value of said address field; an address value providing access to said memory means from said central processing unit having a predetermined priority of operation over an address value defining an instruction to be executed by said video display processor means; and said interpretation means interrupting the operation of one of said instructions being executed by said video display processor means in response to the reception of an address value in said first value range of said address space defined by said address field corresponding to an operation of higher priority.