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Method for fabricating multilayer circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-031/16
출원번호 US-0164452 (1988-03-04)
발명자 / 주소
  • Rellick Joseph R. (Wilmington DE)
출원인 / 주소
  • E. I. Du Pont de Nemours and Company (Wilmington DE 02)
인용정보 피인용 횟수 : 81  인용 특허 : 6

초록

The invention is directed to a method for fabricating multilayer circuits on rigid substrates using conventional dielectric green tape and thick film conductive pastes while maintaining excellent X-Y dimensional stability.

대표청구항

A method for the fabrication of multilayer circuits comprising the sequential steps of: (a) providing a dimensionally stable electrically insulative substrate; (b) applying to the substrate a patterned conductive layer; (c) firing the patterned conductive layer; (d) laminating to the fired patterned

이 특허에 인용된 특허 (6)

  1. Takeuchi Yukihisa (Nagoya JPX) Masumori Hideo (Anjyo JPX), Ceramic composition for dielectrics.
  2. Fujita Tsuyoshi (Yokohama JPX) Taguchi Noriyuki (Yokohama JPX) Toda Gyozo (Hino JPX) Kuroki Takashi (Yokohama JPX) Ishihara Shoosaku (Yokohama JPX), Ceramic wiring boards.
  3. Steinberg Jerry I. (Wilmington DE), Dielectric composition.
  4. Rellick Joseph R. (Wilmington DE), Dielectric compositions and method of forming a multilayer interconnection using same.
  5. Kamehara Nobuo (Isehara JPX) Kurihara Kazuaki (Kawasaki JPX) Niwa Koichi (Tama JPX), Method for producing multilayered glass-ceramic structure with copper-based conductors therein.
  6. Vitriol William A. (Anaheim CA) Brown Raymond L. (Riverside CA), Process for fabricating dimensionally stable interconnect boards.

이 특허를 인용한 특허 (81)

  1. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric and metallization process and semiconductor package.
  2. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.
  3. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.
  4. Huemoeller, Ronald Patrick; Rusli, Sukianto, Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns.
  5. St. Amand, Roger D., Column and stacking balls package fabrication method and structure.
  6. Katsuhiko Hayashi JP, Electronic component for high frequency signals and method for fabricating the same.
  7. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.
  8. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.
  9. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon; Karim, Nozad Osman, Embedded metal features structure.
  10. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Encapsulated semiconductor package.
  11. Hiner, David Jon; Huemoeller, Ronald Patrick, Extended landing pad substrate package structure and method.
  12. Hiner, David Jon; Huemoeller, Ronald Patrick, Extended landing pad substrate package structure and method.
  13. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  14. Bolognia, David; Adlam, Ted; Kelly, Mike, Fingerprint sensor package and method.
  15. Darveaux, Robert Francis; Bancod, Ludovico E.; Mattei, Marnie Ann; Olson, Timothy Lee, Flex circuit package and method.
  16. Sammet Manfred (Calw-Stammheim DEX), Glass-ceramic structure and method for making same.
  17. Leigh William C. ; Deakins Stephen S., High current ferrite electromagnetic interference suppressor and associated method.
  18. Leigh William C. ; Deakins Stephen S., High current ferrite electromagnetic interference supressor and associated method.
  19. Lee, DongHoon; Kim, DoHyung; Park, JungSoo; Han, SeungChul; Kim, JooHyun; Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package.
  20. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Bolognia, David, Light emitting diode (LED) package and method.
  21. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package.
  22. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package and method.
  23. Gantzhorn ; Jr. John E. (Hockessin DE) Nann Steven R. (Newark DE), Method for fabricating multilayer circuits.
  24. Yutaka Tsukada JP; Shuhei Tsuchida JP, Method for making a printed circuit board.
  25. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Method for making an integrated circuit substrate having laminated laser-embedded circuit layers.
  26. Hashimoto, Akira; Nakao, Keiichi; Katsumata, Masaaki, Method for manufacturing ceramic multi-layered board.
  27. Sumiya, Atsuhiro; Yasuda, Eturo; Shindo, Hitoshi; Suzuki, Yasunori; Yamamoto, Takashi; Nagaya, Toshiatsu; Kihara, Noriaki, Method for manufacturing laminated dielectrics.
  28. Yeh Tsung-Shou (Hsinchu TWX) Hwang Shiang-Po (Tainan TWX) Wang Chien-Min (Hsinchu TWX) Ting Chung-Yu (Hsinchu TWX), Method for preparing multilayer ceramic/glass substrates with electromagnetic shielding.
  29. Rusli, Sukianto; Huemoeller, Ronald Patrick, Method of fabricating an embedded circuit pattern.
  30. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  31. Bezama Raschid J. ; Gupta Dinesh ; Natarajan Govindarajan, Method of making a multilayer ceramic product with thin layers.
  32. Haq Samuel F. ; Malone Patrick F. ; Fortney John H. ; Varner Donald P., Method of making ceramic substrate.
  33. Yamamoto, Yoshikatsu; Wada, Takaichi; Takashima, Nagamitsu; Okumura, Motonori; Hara, Kazuhiko; Tanaka, Yuji; Katakura, Takahiro; Watanabe, Kohji, Method of manufacturing an ink-jet recording head using a thermally fusible film that does not close communication holes.
  34. Kohno Yoshiaki (Kyoto JPX) Sakai Norio (Kyoto JPX), Method of manufacturing ceramic laminate.
  35. Okada Yoshitsugu (Tokyo JPX), Method of manufacturing multi-layered wiring substrate.
  36. Nicholls, Louis W.; St. Amand, Roger D.; Kim, Jin Seong; Jung, Woon Kab; Yang, Sung Jin; Darveaux, Robert F., Methods and structures for increasing the allowable die size in TMV packages.
  37. Dreiza, Mahmoud; Ballantine, Andrew; Shumway, Russell Scott, Molded cavity substrate MEMS package fabrication method and structure.
  38. Bergstedt, Leif, Multi-layer circuit board with supporting layers of different materials.
  39. Huemoeller, Ronald Patrick; Hiner, David Jon; Lie, Russ, Multi-level circuit substrate fabrication method.
  40. Bergstedt Leif,SEX, Process for manufacturing a multi-layer circuit board with supporting layers of different materials.
  41. Kim, Do Hyung; Kang, Dae Byoung; Han, Seung Chul, Semiconductor device.
  42. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Ahn, Ye Sul, Semiconductor device and fabricating method thereof.
  43. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  44. Clark, David; Zwenger, Curtis, Semiconductor device and manufacturing method thereof.
  45. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.
  46. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.
  47. Ryu, Ji Yeon; Kim, Byong Jin; Shim, Jae Beum, Semiconductor device and manufacturing method thereof.
  48. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  49. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  50. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  51. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  52. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  53. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  54. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  55. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  56. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  57. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  58. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  59. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  60. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  61. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  62. Bancod, Ludovico E.; Kim, Jin Seong; Wachtler, Kurt Peter, Stackable plasma cleaned via package and method.
  63. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable protruding via package and method.
  64. Darveaux, Robert Francis; Bancod, Ludovico; Yoshida, Akito, Stackable treated via package and method.
  65. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  66. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  67. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  68. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  69. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  70. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  71. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  72. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  73. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Troche, Jr., Louis B.; Syed, Ahmer; Shumway, Russell, Stacked and staggered die MEMS package and method.
  74. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  75. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  76. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  77. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  78. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Substrate having stiffener fabrication method.
  79. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  80. St. Amand, Roger D., Underfill contacting stacking balls package fabrication method and structure.
  81. Jung, Boo Yang; Paek, Jong Sik; Lee, Choon Heung; Park, In Bae; Kim, Sang Won; Kim, Sung Kyu; Lee, Sang Gyu, Wafer level fan out semiconductor device and manufacturing method thereof.
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