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Instruction issuing mechanism for processors with multiple functional units 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0112020 (1987-10-14)
발명자 / 주소
  • Torng Hwa C. (Ithaca NY)
출원인 / 주소
  • Cornell Research Foundation, Inc. (Ithica NY 02)
인용정보 피인용 횟수 : 305  인용 특허 : 6

초록 ▼

An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according

대표청구항 ▼

An instruction issuing system for a processor including an execution unit having multiple functional units comprising: an instruction issuing unit receiving instructions from a memory, operating on instructions and forwarding instructions to said execution unit, said instruction issuing unit includi

이 특허에 인용된 특허 (6)

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  126. Ramagopal H. S. ; Hattangadi Rajiv M. ; Chinnakonda Muralidharan S., Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non.
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  128. Pflum Marty L., Lookahead register value generator and a superscalar microprocessor employing same.
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  130. Witt David B., Map unit having rapid misprediction recovery.
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  133. Griffith James S. (Aloha OR) Gupta Shantanu R. (Beaverton OR) Hinton Glenn J. (Portland OR), Method and apparatus for binding instructions to dispatch ports of a reservation station.
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  138. Tran Thang M., Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions.
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  139. Narayan Rammohan ; Tran Thang M., Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations.
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  142. Christie David S., Method and mechanism for checking integrity of byte enable signals.
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  144. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring efficiency of branch unit operation in a processing system.
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  145. Levine Frank Eliot (Austin TX) Roth Charles Philip (Austin TX) Welbon Edward Hugh (Austin TX), Method and system for performance monitoring of dispatch unit efficiency in a processing system.
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  146. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring of misaligned memory accesses in a processing system.
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  147. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring through identification of frequency and length of time of execution of ser.
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  148. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring time lengths of disabled interrupts in a processing system.
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  150. Narayan Rammohan ; Mahalingaiah Rupaka ; Miller Paul K., Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor.
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  154. Shen,Gene W.; Nelson,S. Craig, MicroTLB and micro tag for reducing power in a processor.
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  158. Narayan Rammohan ; Southard Shane A. ; Tran Thang M., Microcode scan unit for scanning microcode instructions using predecode data.
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  160. Rupaka Mahalingaiah ; Gerald D. Zuraski, Jr., Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same.
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  164. Mahalingaiah Rupaka ; Tran Thang M., Microprocessor having address generation units for efficient generation of memory operation addresses.
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  165. Witt David B. ; Tran Thang M., Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address.
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  174. Narayan Rammohan, Parallel mask decoder and method for generating said mask.
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  180. Witt David B. ; Goddard Michael D., Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions.
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  182. Tran Thang M., Predecode unit adapted for variable byte-length instruction set processors and method of operating the same.
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  184. Tran Thang M., Prefetch buffer which stores a pointer indicating an initial predecode position.
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  190. Witt David B., Processor configured to map logical register numbers to physical register numbers using virtual register numbers.
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  191. Witt David B., Processor configured to map logical register numbers to physical register numbers using virtual register numbers.
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  192. Witt David B., Processor configured to selectively free physical registers upon retirement of instructions.
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  193. Lancaster, John C, Processor controller for accelerating instruction issuing rate.
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  200. Rowlands, Joseph B.; Keller, James B., Programmably disabling one or more cache entries.
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  203. Garg Sanjiy ; Lentz Derek J. ; Nguyen Le Trong ; Chen Sho Long, RISC microprocessor architecture implementing multiple typed register sets.
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  210. Tran Thang M., Recorder buffer capable of detecting dependencies between accesses to a pair of caches.
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  216. Witt David B. ; Tran Thang M., Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions receiv.
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  218. Witt David B. ; Tran Thang M., Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units.
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  219. Tran Thang M. ; Witt David B., Reorder buffer employing last in line indication.
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  220. Tran Thang M., Reorder buffer having a future file for storing speculative instruction execution results.
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  221. Tran Thang M., Reorder buffer having a future file for storing speculative instruction execution results.
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  222. Witt David B. ; Tran Thang M., Reorder buffer having an improved future file for storing speculative instruction execution results.
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  223. Tan Teik-Chung, Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an e.
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  224. Walker Wade A., Reorder buffer which forwards operands independent of storing destination specifiers therein.
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  225. Tran Thang M. ; Mahalingaiah Rupaka, Return address prediction system which adjusts the contents of return stack storage to enable continued prediction afte.
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  226. Witt David B. ; Tran Thang M., Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache.
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  227. Witt David B. ; Tran Thang M., Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache.
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  228. Lynch Thomas W., Ripple carry shifter in a floating point arithmetic unit of a microprocessor.
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  229. Favor John G. ; Ben-Meir Amos ; Trull Jeffrey E., Scan chain for rapidly identifying first or second objects of selected types in a sequential list.
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  230. Christie David S., Segmentation suspend mode for real-time interrupt support.
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  231. Witt David B., Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access.
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  232. McFarland Harold L. ; Stiles David R. ; Van Dyke Korbin S. ; Mehta Shrenik ; Favor John Gregory ; Greenley Dale R. ; Cargnoni Robert A., Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execut.
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  233. Tran Thang M., Shared branch prediction structure.
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  234. Witt David B., Speculative instruction queue and method therefor particularly suitable for variable byte-length instructions.
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  236. Tran Thang M. ; Pickett James K. ; Mahalingaiah Rupaka, Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurr.
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  237. Tran Thang M., Storage device having varying access times and a superscalar microprocessor employing the same.
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  238. Pickett James K., Stride-based data address prediction structure.
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  239. Pickett James K., Stride-based data address prediction structure.
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  240. Garg Sanjiv ; Iadonato Kevin Ray ; Nguyen Le Trong ; Wang Johannes, Superscalar RISC instruction scheduling.
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  241. Garg, Sanjiv; Iadonato, Kevin Ray; Nguyen, Le Trong; Wang, Johannes, Superscalar RISC instruction scheduling.
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  242. Garg,Sanjiv; Iadonato,Kevin Ray; Nguyen,Le Trong; Wang,Johannes, Superscalar RISC instruction scheduling.
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  243. Witt David B. ; Goddard Michael D.,GBX, Superscalar instruction decoder including an instruction queue.
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  244. Tran Thang M. ; Mahalingaiah Rupaka, Superscalar microprocessor configured to predict return addresses from a return stack storage.
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  245. Tran Thang M. ; Mahalingaiah Rupaka, Superscalar microprocessor configured to predict return addresses from a return stack storage.
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  246. Tran Thang M. ; Mahalingaiah Rupaka, Superscalar microprocessor configured to predict return addresses from a return stack storage.
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  247. Witt David B. ; Hattangadi Rajiv M., Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle.
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  248. Witt David B. ; Hattangadi Rajiv M., Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle.
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  249. Tran Thang M. ; Pickett James K., Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to co.
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  250. Coon Brett ; Miyayama Yoshiyuki ; Nguyen Le Trong ; Wang Johannes, Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from.
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  251. Witt David B. ; Tran Thang M., Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of i.
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  252. Pflum Marty L., Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and anothe.
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  253. Tran Thang M., Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions.
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  254. Tran Thang ; Witt David B. ; Johnson William M., Superscalar microprocessor including a high speed instruction alignment unit.
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  255. Tran Thang M. ; Witt David B. ; Johnson William M., Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache.
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  256. Witt David B. ; Tran Thang, Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units.
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  257. White Scott A. (Austin TX) Christie David S. (Austin TX) Goddard Michael D. (Austin TX), Superscalar microprocessor including flag operand renaming and forwarding apparatus.
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  259. Ramagopal H. S. ; Tran Thang M. ; Pickett James K., Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operatio.
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  260. Tran Thang M. ; Witt David B., Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction unti.
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  261. Narayan Rammohan, Superscaler microprocessor employing a parallel mask decoder.
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  262. Iadonato Kevin R. ; Deosaran Trevor A. ; Garg Sanjiv, System and method for assigning tags to control instruction processing in a superscalar processor.
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  263. Iadonato, Kevin R.; Deosaran, Trevor A.; Garg, Sanjiv, System and method for assigning tags to control instruction processing in a superscalar processor.
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  266. Kevin R. Iadonato ; Trevor A. Deosaran ; Sanjiv Garg, System and method for assigning tags to control instruction processing in a superscalar processor.
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  267. Iadonato Kevin Ray ; Deosaran Trevor Anthony ; Garg Sanjiv, System and method for assigning tags to instructions to control instruction execution.
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  268. Christie, David S., System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes.
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  270. Brashears, Cheryl Senter; Wang, Johannes; Nguyen, Le Trong; Lentz, Derek J.; Miyayama, Yoshiyuki; Garg, Sanjiv; Hagiwara, Yasuaki; Lau, Te-Li; Wang, Sze-Shun; Trang, Quang H., System and method for handling load and/or store operations in a superscalar microprocessor.
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  271. Cheryl D. Senter ; Johannes Wang, System and method for handling load and/or store operations in a superscalar microprocessor.
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  276. Senter, Cheryl D.; Wang, Johannes, System and method for handling load and/or store operations in a superscalar microprocessor.
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  277. Senter,Cheryl D.; Wang,Johannes, System and method for handling load and/or store operations in a superscalar microprocessor.
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  278. Senter Cheryl D. ; Wang Johannes, System and method for handling load and/or store operators in a superscalar microprocessor.
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  279. Deosaran Trevor A. ; Garg Sanjiv ; Iadonato Kevin R., System and method for register renaming.
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  280. Deosaran Trevor A. ; Garg Sanjiv ; Iadonato Kevin R., System and method for register renaming.
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  281. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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  283. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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  284. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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  286. Johannes Wang ; Sanjiv Garg ; Trevor Deosaran, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.
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  287. Wang Johannes ; Garg Sanjiv ; Dcosaran Trevor, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.
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  288. Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.
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  290. Coon Brett ; Miyayama Yoshiyuki ; Nguyen Le Trong ; Wang Johannes, System and method for translating non-native instructions to native instructions for processing on a host processor.
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  291. Coon, Brett; Miyayama, Yoshiyuki; Nguyen, Le Trong; Wang, Johannes, System and method for translating non-native instructions to native instructions for processing on a host processor.
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