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A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate

A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate at the upper layers of the surface followed by progressively lower power corresponding lower etch rates at the lower levels of the surface. The etching process is followed by a cleaning process to remove metallic contamination resulting from the plasma etching process to yield an excellent surface for growing low defect density MOS gate oxides with high dielectric integrity.

대표청구항

A method for pregate etching of a metal-oxide-semiconductor (MOS) thin film comprising the steps of: plasma etching said thin film at a first power level; plasma etching said thin film at a second power level, said second power level being lower than said first power level.

A method for pregate etching of a metal-oxide-semiconductor (MOS) thin film comprising the steps of: plasma etching said thin film at a first power level; plasma etching said thin film at a second power level, said second power level being lower than said first power level.