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Semiconductor device having a silicon on insulator structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/46
  • H01L-029/54
  • H01L-029/62
출원번호 US-0922907 (1986-10-24)
우선권정보 JP-0244433 (1985-10-31)
발명자 / 주소
  • Shirato Takehide (Hiratsuka JPX) Aneha Nobuhiko (Yokohama JPX)
출원인 / 주소
  • Fujitsu Limited (Kanagawa JPX 03)
인용정보 피인용 횟수 : 49  인용 특허 : 0

초록

A semiconductor device having an SOI structure comprises an insular single crystal silicon body formed on an insulator layer, a first region of a first type semiconductor and source and drain regions of a second type semiconductor provided in the insular single crystal silicon body so that the first

대표청구항

A semiconductor device having a silicon on insulator structure comprising: an insulator layer; an insular body formed on said insulator layer, said insular body being made of a single crystal silicon doped to a first type semiconductor; a first region of the first type semiconductor provided in said

이 특허를 인용한 특허 (49)

  1. Willard, Simon Edward; Ranta, Tero Tapio, AC coupling modules for bias ladders.
  2. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
  3. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
  4. Mistry Kaizad Rumy ; Sleight Jeffrey William, Compact self-aligned body contact silicon-on-insulator transistors.
  5. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  6. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  7. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
  8. Choi, Byoung-Deog; Bae, Sung-Sik; Kim, Won-Sik, Display device including thin film transistor.
  9. Koo, Jae-Bon; Choi, Byoung-Deog, Flat panel display.
  10. Scott Crowder ; Dominic J. Schepis ; Melanie J. Sherony, Fully amorphized source/drain for leaky junctions.
  11. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
  12. Mukherjee, Satyen, Integrated LED drive electronics on silicon-on-insulator integrated circuits.
  13. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  14. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  15. Blake Terence G. W. (Dallas TX), Making a silicon-on-insulator transistor with selectable body node to source node connection.
  16. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
  17. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  18. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  19. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  20. Osame, Mitsuaki; Miyake, Hiroyuki; Miyazaki, Aya; Yamazaki, Shunpei, Method for deleting data from NAND type nonvolatile memory.
  21. Choi, Byoung-Deog; Bae, Sung-Sik; Kim, Won-Sik, Method of fabricating thin film transistor.
  22. Fechner, Paul S.; Shaw, Gordon A.; Vogt, Eric E., Method of forming a body-tie.
  23. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
  24. Yamazaki, Shunpei; Asami, Yoshinobu; Takano, Tamae; Furuno, Makoto, Nonvolatile semiconductor memory device.
  25. Yamazaki, Shunpei; Asami, Yoshinobu; Takano, Tamae; Furuno, Makoto, Nonvolatile semiconductor memory device.
  26. Yamazaki, Shunpei; Asami, Yoshinobu; Takano, Tamae; Furuno, Makoto, Nonvolatile semiconductor memory device.
  27. Yamazaki, Shunpei; Asami, Yoshinobu; Takano, Tamae; Furuno, Makoto, Nonvolatile semiconductor memory device.
  28. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
  29. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
  30. Bahraman Ali (Palos Verdes Estates CA), Radiation hardened CMOS on SOI or SOS devices.
  31. Ebina, Akihiko, SOI-structure field-effect transistor and method of manufacturing the same.
  32. Shino, Tomoaki, Semiconductor device comprising an insulating mask formed on parts of a gate electrode and semiconductor layer crossing an active region.
  33. Yamazaki, Yasushi, Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment.
  34. Yamazaki, Yasushi, Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment.
  35. Olson, Chris, Semiconductor devices with switchable ground-body connection.
  36. Ohkubo, Tatsuya; Kawachi, Genshiro; Mikami, Yoshiro; Masuda, Kazuhito; Kageyama, Hiroshi, Semiconductor element and liquid crystal display device using the same.
  37. Ohkubo Tatsuya,JPX ; Kawachi Genshiro,JPX ; Mikami Yoshiro,JPX ; Masuda Kazuhito,JPX ; Kageyama Hiroshi,JPX, Semiconductor element with N channel and P region connected only to the channel and liquid crystal display device using the same.
  38. Carroll, Michael; Kerr, Daniel Charles; Iversen, Christian Rye; Mason, Philip; Costa, Julio; Spears, Edward T., Semiconductor radio frequency switch with body contact.
  39. Ohkubo,Tatsuya; Kawachi,Genshiro; Mikami,Yoshiro; Masuda,Kazuhito; Kageyama,Hiroshi, Static RAM having a TFT with n-type source and drain regions and a p-type region in contact with only the intrinsic channel of the same.
  40. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  41. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  42. Bertin Claude Louis ; Ellis-Monaghan John Joseph ; Hedberg Erik Leigh ; Hook Terence Blackwell ; Mandelman Jack Allan ; Nowak Edward Joseph ; Pricer Wilbur David ; Tong Minh Ho ; Tonti William Robert, Switched body SOI (silicon on insulator) circuits and fabrication method therefor.
  43. Koo, Jae-Bon; Choi, Byoung-Deog; So, Myeong-Seob; Kim, Won-Sik, Thin film transistor.
  44. Choi, Byoung-Deog; Bae, Sung-Sik; Kim, Won-Sik, Thin film transistor and display device using the same.
  45. Choi,Byoung Deog; Bae,Sung Sik; Kim,Won Sik, Thin film transistor and display device using the same.
  46. Park, Byoung-Keon, Thin film transistor, method of fabricating the same, and a display device including the thin film transistor.
  47. Park, Byoung-Keon, Thin film transistor, method of fabricating the same, and a display device including the thin film transistor.
  48. Park, Byoung-Keon; Yang, Tae-hoon; Seo, Jin-Wook; Jung, Sei-Hwan; Lee, Ki-Yong, Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same.
  49. Park, Byoung-Keon; Yang, Tae-hoon; Seo, Jin-Wook; Jung, Sei-Hwan; Lee, Ki-Yong, Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same.
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