초록 ▼

A charge pump circuit is integrated form utilizes a dual emitter transistor switch having low saturation voltage. The low saturation voltage for the transistor is provided by deriving a base bias voltage from the doubled voltage (2Vcc) and a collector voltage from the voltage supply (Vcc). Current-l

A charge pump circuit is integrated form utilizes a dual emitter transistor switch having low saturation voltage. The low saturation voltage for the transistor is provided by deriving a base bias voltage from the doubled voltage (2Vcc) and a collector voltage from the voltage supply (Vcc). Current-limiting for the transistor is provided by connecting one emitter to the base bias circuitry whereby the second emitter acts as a collector when the transistor saturates, thereby limiting the base drive and causing current-limiting.

대표청구항 ▼

A charge pump circuit comprising a supply terminal for connecting to a voltage source, Vcc, a ground terminal for connecting to a ground potential, a first capacitor serially connected with first and second switch means between said supply terminal and said ground terminal, a third switch means conn

A charge pump circuit comprising a supply terminal for connecting to a voltage source, Vcc, a ground terminal for connecting to a ground potential, a first capacitor serially connected with first and second switch means between said supply terminal and said ground terminal, a third switch means connected in parallel with said first switch means and said first capacitor, a second capacitor serially connected with fourth and fifth switch means between the common terminal of said first switch means and said first capacitor and said ground terminal, a third capacitor serially connected with a sixth switch means between said ground potential and the common terminal of said first switch means and said first capacitor, the common terminal of said third capacitor and said sixth switch means connected to a positive voltage (+2Vcc) terminal, a fourth capacitor serially connected with a seventh switch means between said ground potential and the common terminal of said second capacitor and said fifth switch means, the common terminal of said fourth capacitor and said seventh switch means connected to a negative voltage (-2Vcc) terminal, and an eighth switch means connected in parallel with said second capacitor and said fifth switch means, whereby closure of said first, second, seventh and eighth switch means during a first operational phase generates a voltage Vcc across said first capacitor, and closure of said third, fourth, fifth and sixth switch means during a second operational phase transfers a voltage +2Vcc to said second and third capcitors, and during a subsequent first operational phase a voltage -2Vcc is transferred to said fourth capacitor.