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A defect detector circuit for an inductive load driving circuit which has a surge comparator circuit for comparing a surge generated from an inductive load when the current of the inductive load is interrupted with a reference value on the basis of an output from a surge absorber circuit for absorbi

A defect detector circuit for an inductive load driving circuit which has a surge comparator circuit for comparing a surge generated from an inductive load when the current of the inductive load is interrupted with a reference value on the basis of an output from a surge absorber circuit for absorbing the surge, and a surge time deciding circuit for outputting a defect signal when a time that the surge amount exceeds the reference value does not fall within a set range on the basis of the output from the surge comparator circuit.

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A defect detector circuit comprising: a surge comparator circuit connected to receive a surge voltage generated from an inductive load and which produces a reference voltage, compares the surge voltage with the reference voltage, and produces a comparator output signal which is in a first logic stat

A defect detector circuit comprising: a surge comparator circuit connected to receive a surge voltage generated from an inductive load and which produces a reference voltage, compares the surge voltage with the reference voltage, and produces a comparator output signal which is in a first logic state during a first time period wherein the surge voltage exceeds the reference voltage, and in a second logic state otherwise; a surge time deciding circuit connected to receive the comparator output signal and including: (a) a first one-shot multivibrator connected to receive the comparator output signal and to produce a first output pulse for a second time period when the comparator output signal changes from the second logic state to the first logic state, and (b) a first flip-flop with a data terminal connected to receive the comparator output signal and a timing terminal connected to receive the first multivibrator output pulse and to store the signal at the data terminal when the first multivibrator output changes from the first logic state to the second logic state, wherein the surge time deciding circuit outputs a signal in a first logic state normally and in a second logic state when a defect causes the first time period to be shorter than the second time period; and a defect indicator circuit connected to indicate a defect in accordance with the output of the surge time deciding circuit.