초록 ▼

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

대표청구항 ▼

A multiprocessor system, comprising: at least three separate processor modules, each processor module including a central processing unit, a main memory and an input/output channel; at least two interprocessor buses, each bus coupling the separate processor modules to one another to transfer signals

A multiprocessor system, comprising: at least three separate processor modules, each processor module including a central processing unit, a main memory and an input/output channel; at least two interprocessor buses, each bus coupling the separate processor modules to one another to transfer signals and data between the processor modules; at least two device controllers operable to control data transfer between the processor modules and at least one related peripheral device connected to each device controller, each device controller including at least two separate ports; a plurality of input/output buses separated from the interprocessor buses, each input/output bus being disposed between the input/output channel of a corresponding processor module and a one of the ports of the device controller so as to connect each device controller with at least two of the processor modules; means in each processor module for transferring through a one of the interprocessor buses to an associated processor module information associated with an application program resident in the processor modules; means in each processor module for sending a predetermined control signal to each other processor module through a one of the interprocessor buses; means in each processor module for detecting when the predetermined control signal has not been received from the other processor module within a predetermined period and determining therefrom that the other processor module has failed; means in each processor module responsive to the detection of the failure of receipt of the predetermined control signal within the predetermined period for initiating execution of a copy of said application program in the detecting processor module to thereby cause the detecting processor module to take over the work of the determined failed processor module; and means in each processor module for controlling the related device controller through the input/output bus to control the related peripheral device so as to provide each of the peripheral devices with simultaneous operations.