초록 ▼

A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a se

A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a second anisotropic etching of part of the silicon nitride to obtain a ladder-shaped polysilicon gate having a silicon nitride thereon; or (2) an anisotropic polysilicon etch step, an isotropic photoresist erosion step to expose part of the unetched polysilicon, and a second anisotropic polysilicon etch step to remove completely the unmasked polysilicon to obtain the ladder-shaped polysilicon gate. The LDD structure is formed by the implantation of ions to form a heavily-doped source and drain regions and lightly-doped regions under the step of the ladder-shaped polysilicon gate layer. Thereafter, the thin polysilicon step is oxidized completely. After the silicon nitride and silicon dioxide layers are removed, the self-aligned silicide may be applied to form the LDD with salicide.

대표청구항 ▼

A process for preparing a structure useful in making a two-region lightly-doped drain field effect transistor which comprises: a. defining a gate pattern by means of a photoresist mask on a silicon dioxide layer of a laminate comprising a semiconductor substrate having deposited thereon successively

A process for preparing a structure useful in making a two-region lightly-doped drain field effect transistor which comprises: a. defining a gate pattern by means of a photoresist mask on a silicon dioxide layer of a laminate comprising a semiconductor substrate having deposited thereon successively a gate oxide layer and a polysilicon layer, and said silicon dioxide layer; b. completely removing unmasked portions of the silicon dioxide layer and partially removing unmasked portions of the polysilicon layer by anisotropically etching said layers and then stripping the photoresist mask; c. depositing a SiO2 layer followed by an anisotropic etch to form oxide sidewall spacers; d. anisotropically etching the unmasked polysilicon layer partially to form a polysilicon layer having a relatively thick central portion and a relatively thin peripheral step; e. again depositing a SiO2 layer followed by an anisotropic etch to form oxide sidewall spacers; f. again anisotropically etching the unmasked polysilicon completely to form a polysilicon layer having a relatively thick central portion and two concentric peripheral steps, said first step being relatively thin with respect to said central portion and said second step being relatively thin with respect to the first step; and g. removing the sidewall spacers. A process as claimed in claim 31 or 32 which comprises the additional step of h. ion-implanting the resultant structure to form simultaneously heavily doped source/drain regions under said exposed portion of said gate oxide layer and two-region lightly-doped source/drain regions under said two peripheral steps of said polysilicon layer, thereby fabricating a two-region lightly-doped drain field effect transistor.