초록 ▼

An address generation system that generates a second address relative to a first address by either incrementing, decrementing, or passing unchanged, as determined by the control digits in a LIT field, the digital number encoded by the most significant bits of the first address and substituting a sel

An address generation system that generates a second address relative to a first address by either incrementing, decrementing, or passing unchanged, as determined by the control digits in a LIT field, the digital number encoded by the most significant bits of the first address and substituting a selected subset of the digits in the LIT field for the least significant bits of the first address. The first address may be the program counter address and the second address the target address of a branch instruction.

대표청구항 ▼

An address generation system of the type that receives a digital (LIT) field and uses the LIT field to generate a second address relative to a first address, the system comprising: an IDP circuit, including an input port, output port and control port, for generating an IDP output signal comprising a

An address generation system of the type that receives a digital (LIT) field and uses the LIT field to generate a second address relative to a first address, the system comprising: an IDP circuit, including an input port, output port and control port, for generating an IDP output signal comprising a given number of bits at its output port, with the value encoded by the IDP output signal equal to the incremented, decremented or passed (unchanged) signal received at the input port as determined by a control code encoded by a control signal received at the control port; means for transferring a selected subset of the most significant bits of said first address to the input port of said IDP circuit, with the number bits in said subset equal to said given number, means for transferring a first selected subset of the binary digits in said LIT field to the control port of said IDP circuit, with the control code encoded by said selected subset determining the value of said IDP output signal; and means, coupled to said IDP circuit, for combining the IDP output signal with a second subset of the bits in the LIT field to form the second address, with the bits of the IDP output signal forming the most significant bits of the second address and with the second subset of bits forming the least significant bits of the second address. *** BRS DOCUMENT BOUNDARY ***