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5-transistor memory cell with known state on power-up

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
  • G11C-011/40
출원번호 US-0201509 (1988-06-02)
발명자 / 주소
  • Hsieh Hung-Cheng (Sunnyvale CA)
출원인 / 주소
  • Xilinx, Incorporated (San Jose CA 02)
인용정보 피인용 횟수 : 65  인용 특허 : 2

초록

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during r

대표청구항

A memory circuit comprising: a first inverter having an input lead and an output lead; a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transistor having a first source/drain, a seco

이 특허에 인용된 특허 (2)

  1. Holzapfel Heinz P. (Mnchen DEX) Michel Petra (Grafing DEX), Gate array arrangement in complementary metal-oxide-semiconductor technology.
  2. Dingwall Andrew G. F. (Bridgewater NJ), Memory organization.

이 특허를 인용한 특허 (65)

  1. McCollum John L., Antifuse programmed PROM cell.
  2. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Circuits and methods for operating a multiplexer array.
  3. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.
  4. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.
  5. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.
  6. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.
  7. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate wide logic functions.
  8. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
  9. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
  10. Voogel Martin L., DRAM configuration in PLDs.
  11. Voogel Martin L., Dynamic memory cell for a programmable logic device.
  12. Lui,Henry Y.; Kabani,Malik; Patel,Rakesh; Hoang,Tim Tri, Enhanced passgate structures for reducing leakage current.
  13. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., FIFO in FPGA having logic elements that include cascadable shift registers.
  14. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.
  15. Bauer Trevor J. ; Young Steven P., FPGA architecture with deep look-up table RAMs.
  16. Bauer Trevor J. ; Young Steven P., FPGA architecture with dual-port deep look-up table RAMS.
  17. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA architecture with offset interconnect lines.
  18. Tavana Danesh ; Yee Wilson K. ; Holen Victor A., FPGA architecture with repeatable titles including routing matrices and logic matrices.
  19. Bauer Trevor J. ; Young Steven P., FPGA architecture with wide function multiplexers.
  20. Iwanczuk Roman ; Young Steven P., FPGA configurable by two types of bitstreams.
  21. Iwanczuk Roman ; Young Steven P. ; Schultz David P., FPGA having fast configuration memory data readback.
  22. Goetting F. Erich, FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses.
  23. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
  24. Bauer Trevor J. ; Young Steven P., FPGA interconnect structure with high-speed high fanout capability.
  25. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, FPGA logic element with variable-length shift register capability.
  26. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.
  27. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
  28. Lien Chuen-Der ; Wu Chau Chin, Five-transistor SRAM cell.
  29. Percey Andrew K. ; Bauer Trevor J. ; Young Steven P., Input/output interconnect circuit for FPGAs.
  30. Steven P. Young ; Kamal Chaudhary ; Trevor J. Bauer, Interconnect structure for a programmable logic device.
  31. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., Interconnect structure for a programmable logic device.
  32. Lee, Andy L., Interconnection switch structures.
  33. Bauer Trevor J., Lookup tables which double as shift registers.
  34. Chapman, Kenneth D., Method and apparatus for de-spreading spread spectrum signals.
  35. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  36. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
  37. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
  38. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  39. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  40. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Multiplexer array with shifted input traces.
  41. Camarota Rafael C., Non-disruptive randomly addressable memory system.
  42. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
  43. Lee,Andy L; Chang,Wanli; McClintock,Cameron; Turner,John E; Johnson,Brian D; Hwang,Chiao Kai; Chang,Richard Y; Cliff,Richard G, Passage structures for use in low-voltage applications.
  44. Lee, Andy L.; Chang, Wanli; McClintock, Cameron; Turner, John E.; Johnson, Brian D.; Hwang, Chiao Kai; Chang, Richard Yen-Hsiang; Cliff, Richard G., Passgate structures for use in low-voltage applications.
  45. Lee, Andy L.; Chang, Wanli; McClintock, Cameron; Turner, John E.; Johnson, Brian D.; Hwang, Chiao Kai; Chang, Richard Yen-Hsiang; Cliff, Richard G., Passgate structures for use in low-voltage applications.
  46. Lee, Andy L; Chang, Wanli; McClintock, Cameron; Turner, John E; Johnson, Brian D; Hwang, Chiao Kai; Chang, Richard Yen Hsiang; Cliff, Richard G, Passgate structures for use in low-voltage applications.
  47. Candelier,Philippe; Lasseuguette,Jean; Fournel,Richard, Pre-written volatile memory cell.
  48. Ong Randy T. ; Young Edel M., Programmable address decoder for programmable logic device.
  49. Shogo Nakaya JP, Programmable function device and memory cell therefor.
  50. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  51. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  52. Hung Lawrence C., Programmable logic device with partially configurable memory cells and a method for configuration.
  53. Yee Wilson K. (Tracy CA), Programmable scan chain testing structure and method.
  54. Lai Fang-shi (Baldwin NY), Reference voltage generator for precharging bit lines of a transistor memory.
  55. Liaw,Jhon Jhy, SRAM cell for soft-error rate reduction and cell stability improvement.
  56. Voss Peter H., SRAM with ROM functionality.
  57. Rodgers T. J. ; Graf ; III W. Alfred, Self-initializing RAM-based programmable device.
  58. Kuroda, Naoki; Yamagami, Yoshinobu, Semiconductor memory device.
  59. Iwanczuk Roman ; Young Steven P., Structure and method for loading narrow frames of data from a wide input bus.
  60. Iwanczuk Roman ; Young Steven P., Structure and method for loading wide frames of data from a narrow input bus.
  61. Trimberger Stephen M., Structure and method for providing additional configuration memories on an FPGA.
  62. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., Structure for optionally cascading shift registers.
  63. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.
  64. New Bernard J. ; Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Wide logic gate implemented in an FPGA configurable logic element.
  65. Frake Scott O. ; Costello Philip D., Write-assisted memory cell and method of operating same.
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