초록 ▼

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-di

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P1, and P2 channels on the L1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

대표청구항 ▼

A digital signal processor for use in a Global Positioning System (GPS) receiver, the receiver of the type receiving a code-modulated signal, providing a digitized signal from said code-modulated signal, generating model delays, generating a model code sequence that is time offset by the model delay

A digital signal processor for use in a Global Positioning System (GPS) receiver, the receiver of the type receiving a code-modulated signal, providing a digitized signal from said code-modulated signal, generating model delays, generating a model code sequence that is time offset by the model delays so that the resulting model code values are closely aligned in time with the received code sequence, and generating model carrier phases that are closely matched to received carrier phase, for accurately measuring the code group delay and carrier phase of the code-modulated signal; the processor comprising: means for generating counter-rotation sinusoids from model phases; means for counter-rotating the carrier phase of the digitized signal with said counter-rotation sinusoids; means for multiplying the counter-rotated signal with the model code values and accumulating the multiplication produces over respective selected time intervals; means for processing the accumulated products to obtain model phase and model delay; and means for modifying model carrier phase to obtain fast feedback models for code group delays.