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Semiconductor device and its manufacture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02B-001/00
출원번호 US-0880832 (1986-07-01)
우선권정보 JP-0180901 (1985-08-16); JP-0180902 (1985-08-16); JP-0287346 (1985-12-19)
발명자 / 주소
  • Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX)
출원인 / 주소
  • Dai-Ichi Seiko Co., Ltd. (JPX 03)
인용정보 피인용 횟수 : 121  인용 특허 : 9

초록

A semiconductor device of the kind wherein one or more semiconductor chips are housed in a plug-in type package. The package is being molded with a printed wiring substrate, head portions of terminals, and a heat sink for semiconductor chip attachment as an integral part of the package. The one surf

대표청구항

A carrier for semiconductor device, comprising; a plug-in type package having one or more semiconductor chips packaged therein; said plug-in type package comprising a flexible printed wiring substrate, electrically conductive terminals attached to said substrate, a heat sink for semiconductor attach

이 특허에 인용된 특허 (9)

  1. Ogihara, Satoru; Takeda, Yukio; Maeda, Kunihiro; Nakamura, Kousuke; Ura, Mitsuru, Electrically insulating silicon carbide sintered body.
  2. Spinelli, Thomas S.; Manns, William G.; Weirauch, Donald F., Electronic circuit interconnection system.
  3. Braun Robert E. (Norristown PA), Hermetic integrated circuit package for high density high power applications.
  4. Lee James C. K. (Los Altos Hills CA), Integrated circuit packaging systems with double surface heat dissipation.
  5. Ikeya Hirotoshi (Yokosuka JPX) Higashi Michiya (Kawasaki JPX), Resin encapsulation type semiconductor device by use of epoxy resin composition.
  6. Stenerson Gary L. (Santa Cruz CA) Miller Thomas J. (Santa Clara CA), Semiconductor chip carrier package with a heat sink.
  7. Dumont, Bernard; Proponet, Christian; Bancelin, Bernard; Brucker, Roland; Bories, Jean-Louis; Klein, Christiane, Structure for assembling complex electronic circuits.
  8. Dohya Akihiro (Tokyo JPX), Substrate having a pattern of an alloy of gold and a noble and a base metal with the pattern isolated by oxides of the n.
  9. Sugishita Nobuyuki (Yokosuka JPX) Ikegami Akira (Yokohama JPX), Thick-film multi-layer wiring board.

이 특허를 인용한 특허 (121)

  1. Liu, Yong; Liu, Yumin; Yang, Hua; Maldo, Tiburcio A.; Rios, Margie T., 3D smart power module.
  2. Goodwin,Paul; Wehrly, Jr.,James Douglas, Active cooling methods and apparatus for modules.
  3. Burns Carmen D., Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package.
  4. Grajcar, Zdenko, Apparatus and methods for thermal management of electronic devices.
  5. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
  6. Barrett Joseph C., Apparatus for dissipating heat from a conductive layer in a circuit board.
  7. Weber Patrick O., Apparatus for encapsulating electronic packages.
  8. Weber Patrick O. (San Jose CA), Apparatus for encapsulating electronic packages.
  9. Wakabayashi, Kenichi; Takayama, Chitoshi; Shiozaki, Tadashi, Apparatus including processor.
  10. Goodwin,Paul, Buffered thin module system and method.
  11. Roeters,Glen E; Ross,Andrew C, CSP chip stack with flex circuit.
  12. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Dowden, Julian; Buchle, Jeff, Chip scale stacking system and method.
  13. John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
  14. Saxelby, Jr., John R.; Hedlund, III, Walter R., Circuit encapsulation.
  15. Szewerenko, Leland; Partridge, Julian; Orris, Ron, Circuit module having force resistant construction.
  16. Szewerenko,Leland; Partridge,Julian; Orris,Ron, Circuit module having force resistant construction.
  17. Szewerenko, Leland; Partridge, Julian; Lieberman, Wayne; Goodwin, Paul, Circuit module turbulence enhancement systems and methods.
  18. Wehrly, Jr.,James Douglas; Wilder,James; Wolfe,Mark; Goodwin,Paul, Circuit module with thermal casing systems.
  19. Cady, James W.; Wehrly, Jr., James Douglas; Goodwin, Paul, Compact module system and method.
  20. DiStefano, Thomas H.; Karavakis, Konstantine; Mitchell, Craig; Smith, John W., Compliant integrated circuit package.
  21. Distefano Thomas H. ; Karavakis Konstantine ; Mitchell Craig ; Smith John W., Compliant integrated circuit package and method of fabricating the same.
  22. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  23. James Douglas Wehrly, Jr., Contact member stacking system and method.
  24. Wehrly, Jr., James Douglas, Contact member stacking system and method.
  25. Isoda, Takeshi; Shinoda, Koji, Device module and method of manufacturing the same.
  26. Cady, James W.; Goodwin, Paul, Die module system.
  27. Cady,James W.; Goodwin,Paul, Die module system.
  28. Baker Don L. (Johnson City NY) Funari Joseph (Vestal NY) Otto William F. (Rochester MN) Sammakia Bahgat G. (Johnson City NY) Stutzman Randall J. (Vestal NY), Electronic assembly with enhanced heat sinking.
  29. Igor Y. Khandros ; Thomas H. Distefano, Face-up semiconductor chip assemblies.
  30. Thomas, John; Rapport, Russell; Washburn, Robert, Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area.
  31. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
  32. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Flex-based circuit module.
  33. Burns,Carmen D.; Roper,David; Cady,James W., Flexible circuit connector for stacked chip module.
  34. Wehrly, Jr., James Douglas; Wilder, James; Goodwin, Paul; Wolfe, Mark, Heat sink for a high capacity thin module system.
  35. Burns Carmen D. (Austin TX), Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method.
  36. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  37. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  38. Goodwin, Paul, High capacity thin module system and method.
  39. Goodwin, Paul, High capacity thin module system and method.
  40. Goodwin,Paul, High capacity thin module system and method.
  41. Burns, Carmen D., High density integrated circuit module.
  42. Burns Carmen D. (Austin TX), High density lead-on-package fabrication method.
  43. Wakabayashi,Kenichi; Takayama,Chitoshi; Shiozaki,Tadashi, Information processing device.
  44. Avis Steven E., Integral lid/clamp for high power transistor.
  45. Hubbard John B. (Watton-on-Thames GB2), Integrated circuit chip carrier.
  46. Burns Carmen D. (Austin TX), Integrated circuit package with overlapped die on a common lead frame.
  47. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  48. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  49. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system and method.
  50. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Integrated circuit stacking system and method.
  51. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Integrated circuit stacking system and method.
  52. Cady,James W.; Wilder,James; Roper,David L.; Rapport,Russell; Wehrly, Jr.,James Douglas; Buchle,Jeffrey Alan, Integrated circuit stacking system and method.
  53. Goodwin,Paul, Inverted CSP stacking system and method.
  54. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  55. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  56. Partridge, Julian; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Low profile stacking system and method.
  57. Partridge,Julian; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas, Low profile stacking system and method.
  58. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  59. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  60. Wehrly, Jr., James Douglas, Memory card and method for devising.
  61. Wehrly, Jr., James Douglas, Memory card and method for devising.
  62. Rapport, Russell; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Buchle, Jeff, Memory expansion and chip scale stacking system and method.
  63. Rapport, Russell; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Buchle, Jeff, Memory expansion and chip scale stacking system and method.
  64. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff, Memory expansion and chip scale stacking system and method.
  65. Rapport, Russell; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Buchle, Jeff, Memory expansion and integrated circuit stacking system and method.
  66. Goodwin, Paul, Memory module system and method.
  67. Biebuyck, Hans; Delamarche, Emmanuel; Geissler, Matthias; Kind, Hannes; Michel, Bruno, Method for printing a catalyst on substrates for electroless deposition.
  68. McCann, Carl D., Method of fabricating integrated circuit pack trays using modules.
  69. DiStefano, Thomas H.; Karavakis, Konstantine; Mitchell, Craig; Smith, John W., Method of making a compliant integrated circuit package.
  70. Isoda, Takeshi; Shinoda, Koji, Method of manufacturing a device module.
  71. Burns Carmen D., Method of manufacturing a surface mount package.
  72. Burns Carmen D., Method of manufacturing a warp resistant thermally conductive circuit package.
  73. Burns Carmen D. (Austin TX), Method of manufacturing an integrated package having a pair of die on a common lead frame.
  74. Pflughaupt,L. Elliott; Gibson,David; Kim,Young Gon; Mitchell,Craig S.; Zohni,Wael; Mohammed,Ilyas, Microelectronic assembly having array including passive elements and interconnects.
  75. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  76. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  77. Partridge, Julian; Roper, David; Goodwin, Paul, Modified core for circuit module system and method.
  78. Roper,David L.; Hart,Curtis; Wilder,James; Bradley,Phill; Cady,James G.; Buchle,Jeff; Wehrly, Jr.,James Douglas, Modularized die stacking system and method.
  79. Goodwin, Paul; Cady, James W., Module thermal management system and method.
  80. Wehrly, Jr., James Douglas; Wolfe, Mark; Goodwin, Paul, Optimized mounting area circuit module system and method.
  81. Mu Albert T. (San Jose CA), Pin grid array package structure.
  82. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system.
  83. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system and method.
  84. Oka, Seiji; Idaka, Shiori; Yoshida, Hiroshi, Power semiconductor device, printed wiring board, and mechanism for connecting the power semiconductor device and the printed wiring board.
  85. Kitagawa, Katsutoshi, Printed wiring board.
  86. Wakabayashi,Kenichi; Takayama,Chitoshi; Shiozaki,Tadashi, Printer apparatus.
  87. Kirchdoerffer Remy,FRX ; Elefteriou Pierre,FRX, Process for the production of an apparatus or instrument by overmolding and apparatus or instrument thus obtained.
  88. Eric P. Dibble ; Eric H. Laine ; Stephen W. MacQuarrie, Process of producing plastic pin grid array.
  89. Wakabayashi,Kenichi; Takayama,Chitoshi; Shiozaki,Tadashi, Processing device.
  90. Wakabayashi, Kenichi; Takayama, Chitoshi; Shiozaki, Tadashi, Processor apparatus.
  91. Lin, Chih-Cheng; Leu, Chyi-Ming; Kuo, Yu-Ju, Release layer, substrate structure, and method for manufacturing flexible electronic device.
  92. Roper, David L.; Wehrly, Jr., Douglas; Wolfe, Mark, Split core circuit module.
  93. Forthun, John A., Stackable chip package with flex carrier.
  94. Isaak,Harlan R., Stackable flex circuit IC package and method of making same.
  95. Szewerenko,Leland; Goodwin,Paul; Wehrly, Jr.,James Douglas, Stackable micropackages and stacked modules.
  96. Wehrly, Jr.,James Douglas, Stacked integrated circuit module.
  97. Partridge, Julian; Wehrly, Jr., James Douglas; Roper, David L.; Villani, Joseph, Stacked module systems.
  98. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  99. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  100. Partridge, Julian; Wehrly, Jr., James Douglas, Stacked module systems and methods.
  101. Partridge,Julian; Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  102. Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  103. Wehrly, Jr., James Douglas, Stacked modules and method.
  104. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.
  105. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S.; Zohni, Wael; Mohammed, Ilyas, Stacked packages.
  106. Burns, Carmen D.; Wilder, James G.; Dowden, Julian, Stacking system and method.
  107. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Stacking system and method.
  108. Roeters,Glen E; Ross,Andrew C, Stacking system and method.
  109. Jessep, Rebecca A.; Boggs, David W.; McCormick, Carolyn; Dungan, John H.; Sato, Daryl A., Standoff devices and methods of using same.
  110. McMillan John R. (Southlake TX) Maslakow William H. (Lewisville TX) Castro Abram M. (Fort Worth TX), Thermally enhanced chip carrier package.
  111. Goodwin, Paul; Cady, James W.; Wehrly, Douglas, Thin module system and method.
  112. Goodwin,Paul, Thin module system and method.
  113. Goodwin,Paul, Thin module system and method.
  114. Burns Carmen D., Three-dimensional warp-resistant integrated circuit module method and apparatus.
  115. Burns Carmen D., Three-dimensional warp-resistant integrated circuit module method and apparatus.
  116. Weber Patrick O. (San Jose CA) Brueggeman Michael A. (Mountain View CA), Transfer modlded electronic package having a passage means.
  117. Burns Carmen D., Ultra high density integrated circuit packages.
  118. Burns Carmen D., Ultra high density integrated circuit packages.
  119. Burns Carmen D., Ultra high density integrated circuit packages.
  120. Burns Carmen D. ; Cady James W. ; Roane Jerry M. ; Troetschel Phillip Randall, Warp-resistent ultra-thin integrated circuit package fabrication method.
  121. Burns Carmen D., Wrap-resistant ultra-thin integrated circuit package fabrication method.
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