초록 ▼

An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions,

An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500 Åthick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600 Å, removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100°-1200°C. over both the substrate and first polysilicon layer, depositing a second polysilicon gate layer and selectively etching away the layers to form first the device gates and second memory all gate from the second polysilicon layer, and then the floating gate from the first polysilicon layer using the second gate as a self-aligning mask. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass and intermetal layers by means of glass reflow and planarization and wet/dry etching of the intermetal layer.

대표청구항 ▼

An EPROM fabrication process comprising, forming N-channel and P-channel MOS devices in a wafer substrate, said MOS devices having gates, sources and drains associated therewith, forming at least one memory cell device in said wafer substrate, said memory cell device having a floating gate and a sec

An EPROM fabrication process comprising, forming N-channel and P-channel MOS devices in a wafer substrate, said MOS devices having gates, sources and drains associated therewith, forming at least one memory cell device in said wafer substrate, said memory cell device having a floating gate and a second gate above said floating gate, depositing a covering of boron and phosphorus doped silica glass over said MOS and memory cell devices, forming contact holes in said covering leading to selected sources, drains and gates of said MOS and memory cell devices, heating said glass covering to a flow temperature to reflow said glass and to round the corners of said contact holes, depositing a first layer of conductive material over said covering, said material filling said contact holes, selectively etching said first layer to form first conductive lines, forming a first layer of electrically insulative material over said first conductive lines, said insulative layer being formed with a substantially planar surface, forming via holes in said insulative layer to selected first conductive lines, depositing a second layer of conductive material over said insulative layer, said material filling said via holes, and selectively etching said second layer to form second conductive lines.