초록 ▼

A digital motor control system includes a flip-flop latch for receiving motor circuit drive data from a microprocessor, a counter for counting to a predetermined value representing the total duration of a motor drive pulse, a comparator for comparing the incrementing counter value with the motor cir

A digital motor control system includes a flip-flop latch for receiving motor circuit drive data from a microprocessor, a counter for counting to a predetermined value representing the total duration of a motor drive pulse, a comparator for comparing the incrementing counter value with the motor circuit drive data stored in the latch to provide a pulse width modulated signal, delay circuitry for preventing overlapping of motor brake and motor drive signals, a drive gate controlled in part by said pulse width modulated signal for applying a drive signal for motor control, and a brake gate for applying a brake signal for motor control.

대표청구항 ▼

A digital motor control system comprising: clock signal means; storage means for receiving digital motor operation data; latch means coupled to said storage means for receiving and retaining said digital motor operation data; counter means controlled by said clock signal means for counting increment

A digital motor control system comprising: clock signal means; storage means for receiving digital motor operation data; latch means coupled to said storage means for receiving and retaining said digital motor operation data; counter means controlled by said clock signal means for counting incrementally from a first digital value to a second digital value and then returning to said first digital value; digital comparator means coupled to said latch means and to said counter means for comparing the digital value of data stored in said latch means with the digital value stored in said counter means and for providing an output signal on an output thereof when a predetermined relationship occurs between said latch means data value and said counter value; shift means coupled to said clock signal means and said comparator means for time-shifting the output signal from the comparator means; microprocessor means for producing a motor drive signal; motor drive control means coupled to said microprocessor means; reset control means; delay means coupled to said motor drive control means for producing a delayed output signal; first gating means coupled to said shift means, said motor drive control means, and said delay means for controlling said motor drive control signal; and second gating means coupled to said reset control means, said motor drive control means, and said delay means for producing a brake signal which is delayed a predetermined amount in commencing until after a preceding motor drive signal has terminated, said motor drive signal being delayed a predetermined amount in commencing until after a preceding brake signal has terminated.