초록 ▼

A flip-flop circuit which requires only a small drive power and which operates with small power consumption, and in which the on-off transition occurs reliably. The flip-flop circuit comprises MOS field effect transistors (abbreviated as MOSFET\s) and resistors. A first MOSFET and a second MOSFET, t

A flip-flop circuit which requires only a small drive power and which operates with small power consumption, and in which the on-off transition occurs reliably. The flip-flop circuit comprises MOS field effect transistors (abbreviated as MOSFET\s) and resistors. A first MOSFET and a second MOSFET, to which control signals are applied, are commonly-connected at their sources to be connected at the sources to a voltage source supplying a power supply voltage sufficiently higher than a threshold voltage of a third MOSFET and a fourth MOSFET interconnected to each other. The interconnected third and fourth MOSFET\s are connected at their gates to the drains of the first and second MOSFET\s, respectively, and to the drains of the fourth and third MOSFET\s through resistors, respectively. The third and fourth MOSFET\s are common-connected at their sources. An output terminal is led out from the drains of the first and third MOSFET\s.

대표청구항 ▼

A flip-flop circuit comprising: a first field effect transistor of a first conductivity type to the gate of which an input signal of a first polarity is applied; a second field effect transistor of a first conductivity type to the gate of which an input signal of a second polarity opposite to said f

A flip-flop circuit comprising: a first field effect transistor of a first conductivity type to the gate of which an input signal of a first polarity is applied; a second field effect transistor of a first conductivity type to the gate of which an input signal of a second polarity opposite to said first polarity is applied; a third and a fourth field effect transistor both of a second conductivity type having their sources electrically connected with each other, said first and said second field effect transistor having their sources commonly connected, said third and said fourth field effect transistor having their gates connected with a drain of said second and of said first field effect transistor, respectively, an output terminal provided on a connection between the gate of said fourth field effect transistor and a drain of said third field effect transistor, a first resistor along said connection between the gate of said fourth field effect transistor and the drain of said third field effect transistor; and a second resistor connected between the gate of said third field effect transistor and a drain of said fourth field effect transistor.