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Ceramic package for high frequency semiconductor devices

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-023/16
  • H01L-039/02
출원번호 US-0205040 (1988-06-07)
발명자 / 주소
  • Phy William S. (Los Altos CA) Early James M. (Palo Alto CA) Negus Kevien J. (Kingston CAX)
출원인 / 주소
  • Fairchild Semiconductor Corporation (Cupertino CA 02)
인용정보 피인용 횟수 : 84  인용 특허 : 6

초록

A ceramic semiconductor package suitable for high frequency operation includes internal and external ground planes formed on opposite faces of a ceramic base member. The internal ground plane is connected to a ground ring formed on the packaged semiconductor device, and both ground planes are interc

대표청구항

A ceramic semiconductor package comprising: a ceramic base having parallel faces and a peripheral edge between said faces, wherein a first of said faces includes a site for attaching a semiconductor device; an internal ground plane formed on said first of said faces and extending substantially from

이 특허에 인용된 특허 (6)

  1. Gogal John F. (Lebanon NJ), Double cavity semiconductor chip carrier.
  2. Currie, Thomas P., Integrated circuit package with integral heating circuit.
  3. Gilbert, Barry K.; Schwab, Daniel J., Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation.
  4. Schroeder Jack A. (Scottsdale AZ) Winkler Ernel R. (Mesa AZ), Metallization and bonding means and method for VLSI packages.
  5. Stenerson Gary L. (Santa Cruz CA) Miller Thomas J. (Santa Clara CA), Semiconductor chip carrier package with a heat sink.
  6. Miyamoto Takashi (Tokyo JPX), Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied.

이 특허를 인용한 특허 (84)

  1. Burns Carmen D., Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package.
  2. Roeters,Glen E; Ross,Andrew C, CSP chip stack with flex circuit.
  3. Elbanhawy, Alan; Tjia, Benny, Chip module for complete power train.
  4. Elbanhawy, Alan; Tjia, Benny, Chip module for complete power train.
  5. Szewerenko, Leland; Partridge, Julian; Orris, Ron, Circuit module having force resistant construction.
  6. Szewerenko,Leland; Partridge,Julian; Orris,Ron, Circuit module having force resistant construction.
  7. James Douglas Wehrly, Jr., Contact member stacking system and method.
  8. Wehrly, Jr., James Douglas, Contact member stacking system and method.
  9. Liu, Yong; Yuan, Zhongfa, Die package including substrate with molded device.
  10. Liu, Yong; Yuan, Zhongfa, Die package including substrate with molded device.
  11. Lo Verde, Domenico; Bruno, Giuseppe, Electric connection structure for electronic power devices, and method of connection.
  12. Liu, Yong; Qian, Qiuxiao; Liu, Yumin, Embedded semiconductor power modules and packages.
  13. Quinones, Maria Clemens Y.; Gomez, Jocel P., Flex chip connector for semiconductor device.
  14. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
  15. Quinones, Maria Clemens Y.; Gomez, Jocel P., Flex clip connector for semiconductor device.
  16. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Flex-based circuit module.
  17. Burns,Carmen D.; Roper,David; Cady,James W., Flexible circuit connector for stacked chip module.
  18. Wehrly, Jr., James Douglas; Wilder, James; Goodwin, Paul; Wolfe, Mark, Heat sink for a high capacity thin module system.
  19. Hubbard Douglas A. (Canoga Park CA) Gates ; Jr. Louis E. (Westlake Village CA), Hermetic package for integrated circuit chips.
  20. Burns Carmen D. (Austin TX), Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method.
  21. Burns, Carmen D., High density integrated circuit module.
  22. Burns Carmen D. (Austin TX), High density lead-on-package fabrication method.
  23. Oku Akihiro (Kawasaki JPX) Aonuma Souichi (Kawasaki JPX) Wakabayashi Tetsushi (Yokohama JPX), Integrated circuit device having an improved package structure.
  24. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  25. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  26. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Integrated circuit stacking system and method.
  27. Cady,James W.; Wilder,James; Roper,David L.; Rapport,Russell; Wehrly, Jr.,James Douglas; Buchle,Jeffrey Alan, Integrated circuit stacking system and method.
  28. Goodwin,Paul, Inverted CSP stacking system and method.
  29. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  30. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  31. Partridge, Julian; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Low profile stacking system and method.
  32. Partridge,Julian; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas, Low profile stacking system and method.
  33. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff, Memory expansion and chip scale stacking system and method.
  34. Rapport, Russell; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Buchle, Jeff, Memory expansion and integrated circuit stacking system and method.
  35. Burns Carmen D., Method of forming a hermetically sealed circuit lead-on package.
  36. Burns Carmen D., Method of manufacturing a surface mount package.
  37. Burns Carmen D., Method of manufacturing a warp resistant thermally conductive circuit package.
  38. Crane, Jr., Stanford W.; Alcaria, Vicente D.; Jeon, Myoung-Soo, Micro grid array semiconductor die package.
  39. Roper,David L.; Hart,Curtis; Wilder,James; Bradley,Phill; Cady,James G.; Buchle,Jeff; Wehrly, Jr.,James Douglas, Modularized die stacking system and method.
  40. Lee, Jeongil; Lee, Myoungho; Dosdos, Bigildis; Suico, Charles; Edwin, Lee Man Fai; Lim, David Chong Sook; Vilas-Boas, Adriano M., Multi-chip module for battery power control.
  41. Bhattacharyya Bidyut K. ; Mallik Debendra ; Vitt Ron ; Kline David B., Multilayer molded plastic package design.
  42. Choi, Yoon Hwa; Kwon, Yong Suk; Quinones, Maria Clemens Y., Optical coupler package.
  43. Grey, David, Package with multiple dies.
  44. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system.
  45. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system and method.
  46. Yang, Gwi-gyeon, Power device package and method of fabricating the same.
  47. Gomez, Jocel P., Self locking and aligning clip structure for semiconductor die package.
  48. Masuri Kenji,JPX ; Hosoi Yoshihiro,JPX ; Kojima Hisashi,JPX ; Imuta Kazuhito,JPX ; Matsumoto Hiroshi,JPX, Semiconductor device having improved heat resistance.
  49. Liu, Yong; Ju, Jeff; Yuan, Zhongfa; Luo, Roger, Semiconductor die package including embedded flip chip.
  50. Madrid, Ruben, Semiconductor die package including leadframe with die attach pad with folded edge.
  51. Quinones, Maria Clemens Y.; Estacio, Maria Cristina B., Semiconductor die package including low stress configuration.
  52. Quinones, Maria Clemens Y.; Estacio, Maria Cristina B., Semiconductor die package including low stress configuration.
  53. Liu, Yong; Qian, Qiuxiao, Semiconductor die package including multiple semiconductor dice.
  54. Lee, SangDo; Maldo, Tiburcio A., Semiconductor die package including stacked dice and heat sink structures.
  55. Madrid, Ruben P., Semiconductor die package with clip interconnection.
  56. Liu, Yong; Zhu, Zhengyu; Yuan, Zhongfa, Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice.
  57. Yilmaz, Hamza; Sapp, Steven; Wang, Qi; Li, Minhua; Murphy, James J.; Diroll, John Robert, Semiconductor die packages using thin dies and metal substrates.
  58. Tostado Salvador A. ; Brathwaite George A. ; Hoffman Paul R. ; Erfe George A. ; Pedron ; Jr. Serafin P. ; Raftery Michael A. ; Ramakrishna Kambhampati ; Ramirez German J. ; Strauman Linda E., Semiconductor package having a ground or power ring and a metal substrate.
  59. Azotea James K. ; Arthur Steve ; Glascock Homer, Semiconductor power pack.
  60. Forthun, John A., Stackable chip package with flex carrier.
  61. Isaak,Harlan R., Stackable flex circuit IC package and method of making same.
  62. Liu, Yong; Liu, Yumin, Stacked micro optocouplers and methods of making the same.
  63. Partridge, Julian; Wehrly, Jr., James Douglas; Roper, David L.; Villani, Joseph, Stacked module systems.
  64. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  65. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  66. Partridge, Julian; Wehrly, Jr., James Douglas, Stacked module systems and methods.
  67. Partridge,Julian; Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  68. Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  69. Wehrly, Jr., James Douglas, Stacked modules and method.
  70. Burns, Carmen D.; Wilder, James G.; Dowden, Julian, Stacking system and method.
  71. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Stacking system and method.
  72. Roeters,Glen E; Ross,Andrew C, Stacking system and method.
  73. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  74. Luvara John J. ; Quigley ; Jr. John J. ; Prasad Ray, Structure for printed circuit design.
  75. Luvara John J. ; Quigley Jay J ; Prasad Ray, Structure for printed circuit design.
  76. Burns Carmen D., Three-dimensional warp-resistant integrated circuit module method and apparatus.
  77. Burns Carmen D., Three-dimensional warp-resistant integrated circuit module method and apparatus.
  78. Burns Carmen D., Ultra high density integrated circuit packages.
  79. Burns Carmen D., Ultra high density integrated circuit packages.
  80. Burns Carmen D., Ultra high density integrated circuit packages.
  81. Burns Carmen D. ; Cady James W. ; Roane Jerry M. ; Troetschel Phillip Randall, Warp-resistent ultra-thin integrated circuit package fabrication method.
  82. Tao, Su; Yee, Kuo Chung; Kao, Jen Chieh; Chen, Chih Lung; Liau, Hsing Jung, Water-level package with bump ring.
  83. Nishimura, Sadahiro, Wiring substrate.
  84. Burns Carmen D., Wrap-resistant ultra-thin integrated circuit package fabrication method.
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