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Interconnect for layered integrated circuit assembly 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0298806 (1989-01-17)
발명자 / 주소
  • Bezuk Steve J. (Inver Grove Heights MN) Gheewala Tushar R. (Eagan MN) Campbell Stephen A. (Woodbury MN) Baseman Robert J. (Pleasantville NY)
출원인 / 주소
  • Unisys Corporation (Blue Bell PA 02)
인용정보 피인용 횟수 : 24  인용 특허 : 4

초록

Enhanced density of electrical and/or mechanical interconnections between adjacent wafers within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions, is attained by utilizing laser assisted chemical vapor deposition to fabricate preci

대표청구항

A layered, integrated circuit assembly, comprising: a substrate having a planar major surface; electrical conductors lying on said major surface; elongated metal posts which have a first end connected to said conductors and which extend therefrom substantially perpendicular to said major surface; ea

이 특허에 인용된 특허 (4)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  2. Hayakawa Masao (Kyoto JPX) Maeda Takamichi (Nara JPX) Kumura Masao (Nara JPX), Lead electrode structure for a semiconductor chip carried on a flexible carrier.
  3. Lakritz, Mark N.; Ordonez, Jose; Tubiola, Peter J., Method for forming elongated solder connections between a semiconductor device and a supporting substrate.
  4. Warwick William Arthur (Winchester EN), Semiconductor integrated circuit devices.

이 특허를 인용한 특허 (24)

  1. Lo, Jian-Wen; Chen, Chien-Fan, Chip having a metal pillar structure.
  2. Wojnarowski Robert John, Flexible interface structures for electronic devices.
  3. Wojnarowski Robert John, Flexible interface structures for electronic devices.
  4. Roy, Apurba, I-channel surface-mount connector with extended flanges.
  5. Roy, Apurba, I-channel surface-mount connector with extended flanges.
  6. Tsukamoto Kenji (Tokyo JPX), Interconnection structure of electronic parts.
  7. Wojnarowski Robert John ; Whitmore Barry Scott ; Gorowitz Bernard, Interface structures for electronic devices.
  8. Buchwalter,Leena Paivikki; Budd,Russell A.; Patel,Chirag S., Method to create flexible connections for integrated circuits.
  9. Wojnarowski Robert John ; Whitmore Barry Scott ; Gorowitz Bernard, Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas.
  10. Lu, Minhua; Pefecto, Eric D.; Questad, David L.; Ray, Sudipta K., Robust FBEOL and UBM structure of C4 interconnects.
  11. Lu, Minhua; Pefecto, Eric D.; Questad, David L.; Ray, Sudipta K., Robust FBEOL and UBM structure of C4 interconnects.
  12. Lin, How; Egitto, Frank; Markovich, Voya, Semi-conductor chip with compressible contact structure and electronic package utilizing same.
  13. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  14. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  15. Lo, Jian-Wen; Chen, Chien-Fan, Semiconductor device.
  16. Wang, Sheng-Ming; Feng, Hsiang-Ming; Kuo, Yen-Hua, Semiconductor package substrates having layered circuit segments, and related methods.
  17. Shih, Meng-Kai; Lee, Chang-Chi, Semiconductor package with integrated metal pillars and manufacturing methods thereof.
  18. Acocella, John; Banks, Donald Ray; Benenati, Joseph Angelo; Caulfield, Thomas; Hoebener, Karl Grant; Watson, David P.; Corbin, Jr., John Saunders, Solder ball connections and assembly process.
  19. Acocella John (Hopewell Junction NY) Banks Donald R. (Pflugerville TX) Benenati Joseph A. (Hopewell Junction NY) Caulfield Thomas (Croton Fall NY) Hoebener Karl G. (Georgetown TX) Watson David P. (Be, Solder ball interconnected assembly.
  20. Weng, Cheng-Yi, Stacked semiconductor packages and related methods.
  21. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  22. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  23. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  24. Kishi Matsuo,JPX ; Nemoto Hirohiko,JPX ; Okano Hiroshi,JPX, Thermoelectric device and a method of manufacturing thereof.
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