초록 ▼

Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulat

Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer 21 is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding.

대표청구항 ▼

A substrate for interconnecting a plurality of integrated circuits: a base wafer; a first power plane deposited on said base wafer; a thin dielectric plane deposited on said first power plane layer; a second power plane deposited on said dielectric plane layer; said first power plane, said dielectri

A substrate for interconnecting a plurality of integrated circuits: a base wafer; a first power plane deposited on said base wafer; a thin dielectric plane deposited on said first power plane layer; a second power plane deposited on said dielectric plane layer; said first power plane, said dielectric plane and said second power plane forming a wafer wide power plane capacitor across the surface of said wafer in which one of said first and second power planes provides a voltage plane and the other of said first and second power planes provides a ground plane; one of said power planes being more electrically resistive than the other of said power planes, and the thickness of said dielectric layer being smaller than at least one of said power planes to increase the capacitance between said power planes; and a multi-layer interconnection network of conductive signal lines disposed on said wafer wide power plane capacitor for interconnecting a plurality of integrated circuits.