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In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel.

In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.

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Apparatus for executing a floating point arithmetic operation on floating point operands, each floating point operand including a plurality of floating point operand portions, said apparatus comprising: arithmetic logic means for performing an arithmetic operation on a first portion of a first float

Apparatus for executing a floating point arithmetic operation on floating point operands, each floating point operand including a plurality of floating point operand portions, said apparatus comprising: arithmetic logic means for performing an arithmetic operation on a first portion of a first floating point operand and a first portion of a second floating point operand to provide at least a first intermediate result, wherein said arithmetic operation is determined by an executing floating point arithmetic operation; first adder means for combining at least two intermediate operands, wherein said executing operation selects when said two intermediate operands are said first intermediate result and a second intermediate result and when said two intermediate operands are a second portion of said first floating point operand and a second portion of said second floating point operand, said first adder means further combining a rounding signal with said two intermediate operands for a predetermined executing operation; second adder means for combining simultaneously with first adder means said at least two intermediate operands wherein each of said intermediate operands has been multiplied by a scaling factor, said scaling factor determined by said executing operation, said second adding means further combining a rounding constant with said two intermediate operands multiplied by a scaling factor for said predetermined executing operation; and selection means for selecting a first adder means result operand or a second adder means result operand, said executing operation determining when said selection means is controlled by a signal from a one of said first and second adder means and when said selection means is controlled by a signal from said arithmetic means.