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In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cell

In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n×16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

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In a cellular array employing a plurality of processor cells arranged in an X/Y matrix with each of said cells connected to other cells to allow data transfer to the left or right or horizontally or vertically, the improvement therewith comprising: each of the processor cells in one row being config

In a cellular array employing a plurality of processor cells arranged in an X/Y matrix with each of said cells connected to other cells to allow data transfer to the left or right or horizontally or vertically, the improvement therewith comprising: each of the processor cells in one row being configured to operate on data N bits wide; a common bus for said row capable of propagating data 2N bits wide with a first number of bits manifesting a first bus portion and a second number of bits manifesting a second bus portion, said first and second portions of said bus being connected to each of said processing cells in said row, wherein each of said processing cells is capable of transferring and receiving data N bits wide to and from either one of said first and second bus portions of said common bus; and instruction means connected to each of said processing cells in said row for selectively providing an instruction to each process cell to select a mode in which said processor cell transfers and receives data N bits wide to and from one of said first bus portion or said second bus portion; logic means associated with each of said processor cells in said row which is operative in response to a respective instruction provided by said instruction means to cause the respective processor cell to transfer and receive data from said common bus on either said first bus portion or said second bus portion according to its respective selected mode.