초록 ▼

A code converter has a network of logic circuits connected in reverse binary tree fashion with logic paths between leaf nodes and a common root node. Characters are compressed from standard codes to variable-length Huffman code by pulse applying connections to the paths from a decoder. An OR-gate is

A code converter has a network of logic circuits connected in reverse binary tree fashion with logic paths between leaf nodes and a common root node. Characters are compressed from standard codes to variable-length Huffman code by pulse applying connections to the paths from a decoder. An OR-gate is connected to “1”branches of the network to deliver the output code. Characters are decompressed from Huffman to standard codes by connection of the Huffman code to control the clocked logic circuits to deliver a pulse from the root node to one of the inputs of an encoder. A feedback loop connects the root node and the path end nodes to initiate the next conversion. Alternative embodiments have decoder staging to minimize delay and parallel compressed code output.

대표청구항 ▼

A code converter for converting binary signal representations of characters between representations of said character in a first coding scheme and representations of said characters in a second variable-length coding scheme, comprising: a logic network comprising a plurality of logic circuit element

A code converter for converting binary signal representations of characters between representations of said character in a first coding scheme and representations of said characters in a second variable-length coding scheme, comprising: a logic network comprising a plurality of logic circuit elements connected together in reverse binary tree-like fashion to form a plurality of logic paths extending between an element in a common root node position and elements in other node positions which corresponds to different ones of said plurality of characters; input means for passing electrical signals for processing by said elements along said logic paths in accordance with a character signal representation in one of the first and second coding means, said input means comprising a decoder having an input and a plurality of output terminals, with each output terminal connected to a respective one of said elements in said other node positions; output means for receiving electrical signals from said logic elements along said logic paths in the form of representation of the character in the other of said first and second coding schemes, said output means comprising means for receiving output signals from said connections between elements along said logic paths that correspond to “1”branches of a reverse binary tree corresponding to said logic network; and a buffer for storing one of said sequence of character representations in said first coding scheme prior to conversion, and means responsive to completion of the conversion of another of said sequence of character representations for transferring said one of said sequence of character representations to said decoder input for conversion.