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Full panel electronic packaging structure

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0151382 (1988-02-02)
발명자 / 주소
  • Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY) Seraphim Donald P. (Vestal NY) Toole Patrick A. (Westport CT)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 55  인용 특허 : 13

초록

An electronic packaging structure, and a method of making this structure, are disclosed. The electronic packaging structure comprises a full panel, circuitized flexible film semiconductor chip carrier mounted on a circuitized substrate such as a printed circuit board. A plurality of semiconductor ch

대표청구항

An electronic packaging structure comprising: a circuitized substrate having a plurality of bonding sites arranged in a selected pattern on said circuitized substrate; a heat sink which is part of the circuitized substrate; a thermally conductive frame in thermal contact with the heat sink; a flexib

이 특허에 인용된 특허 (13)

  1. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Electronic package assembly method.
  2. Clementi Robert J. (Binghamton NY) Gazdik Charles E. (Endicott NY) Lafer William (Chenango Bridge NY) Lovesky Roy L. (Vestal NY) McBride Donald G. (Binghamton NY) Munson Joel V. (Port Crane NY) Skarv, Flexible film semiconductor chip carrier.
  3. Ecker Mario E. (Poughkeepsie NY) Olson Leonard T. (Jericho VT), High density interconnection means for chip carriers.
  4. Ecker Mario E. (Poughkeepsie NY) Olson Leonard T. (Jericho VT), Integrated circuit package.
  5. Gursky Michael T. (Allentown PA), Method of bonding semiconductor devices to carrier tapes.
  6. Burns Carmen D. (San Jose CA), Method of making gang bonding interconnect tape for semiconductive devices.
  7. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Multi-layer flexible film module.
  8. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Multi-layer flexible film module.
  9. Hamlin, Arthur Houser, Precision registration system for leads.
  10. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  11. Ecker, Mario E.; Olson, Leonard T., Repairable multi-level overlay system for semiconductor device.
  12. Proebsting Robert J. (Dallas TX), Single layer burn-in tape for integrated circuit.
  13. Badet Bernard (Rosny-sous-Bois FRX) Guillaume Francois (St Leu la Foret FRX) Kurzweil Karel (Eaubonne FRX), Standardized information card.

이 특허를 인용한 특허 (55)

  1. Leedy, Glenn J, Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer.
  2. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  3. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  4. DiStefano, Thomas H.; Karavakis, Konstantine; Mitchell, Craig; Smith, John W., Compliant integrated circuit package.
  5. Distefano Thomas H. ; Karavakis Konstantine ; Mitchell Craig ; Smith John W., Compliant integrated circuit package and method of fabricating the same.
  6. Barrow Michael, Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package.
  7. Shibata Kazutaka,JPX ; Horio Tomoharu,JPX, Encapsulated semiconductor device and electronic circuit board mounting same.
  8. Glovatsky Andrew Zachary ; Nation Brenda Joyce ; Schweitzer Charles Frederick ; Dailey Daniel Phillip ; Li Delin ; Baker Jay DeAvis ; Goenka Lakhi Nandlal ; Kneisel Lawrence LeRoy ; Lemecha Myron, Environmentally-sealed electronic assembly and method of making same.
  9. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  10. Igor Y. Khandros ; Thomas H. Distefano, Face-up semiconductor chip assemblies.
  11. Borowiec Joseph A. ; Picot Walter J., Flexible thermal conductor with electromagnetic interference shielding capability for electronic components.
  12. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  13. Westberg David,SEX, Method and an arrangement for the electrical contact of components.
  14. Seah, Alvin; Fernandez, Elstan Anthony, Method for connecting a die assembly to a substrate in an integrated circuit.
  15. Seah, Alvin; Fernandez, Elstan Anthony, Method for connecting a die assembly to a substrate in an integrated circuit and a semiconductor device comprising a die assembly.
  16. Lorenz, Leo; Kaindl, Michael; Schwarzbauer, Herbert; Munzing, Gerhard; Stern, Peter; Bruckmann, Manfred, Method for producing a microelectronic component of sandwich construction.
  17. Goenka Lakhi Nandlal ; Li Delin ; Dailey Daniel Phillip ; Schweitzer Charles Frederick ; Bednarz Michael ; Nation Brenda Joyce, Method for protecting electronic components.
  18. DiStefano, Thomas H.; Karavakis, Konstantine; Mitchell, Craig; Smith, John W., Method of making a compliant integrated circuit package.
  19. Igor Y. Khandros ; Thomas H. Distefano, Methods of making semiconductor chip assemblies.
  20. Khandros Igor Y. ; Distefano Thomas H., Methods of making semiconductor chip assemblies.
  21. Pflughaupt,L. Elliott; Gibson,David; Kim,Young Gon; Mitchell,Craig S.; Zohni,Wael; Mohammed,Ilyas, Microelectronic assembly having array including passive elements and interconnects.
  22. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  23. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  24. Lorenz Leo,DEX ; Kaindl Michael,DEX ; Schwarzbauer Herbert,DEX ; Munzing Gerhard,GBX ; Stern Peter,DEX ; Bruckmann Manfred,DEX, Microelectronic component of sandwich construction.
  25. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  26. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  27. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Semiconductor chip assemblies, methods of making same and components for same.
  28. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  29. Khandros,Igor Y.; Distefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  30. Igor Y. Khandros ; Thomas H. DiStefano, Semiconductor chip assembly with anisotropic conductive adhesive connections.
  31. Khandros Igor Y. ; Distefano Thomas H., Semiconductor chip package with center contacts.
  32. Murayama Kei,JPX, Semiconductor device having circuit pattern along outer periphery of sealing resin and related processes.
  33. Kishida Satoru (Itami JPX), Semiconductor integrated circuit device.
  34. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  35. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
  36. Leedy, Glenn J., Stacked integrated memory device.
  37. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.
  38. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S.; Zohni, Wael; Mohammed, Ilyas, Stacked packages.
  39. Wagner,Sigurd; Lacour,Stephanie Perichon; Suo,Zhigang, Stretchable and elastic interconnects.
  40. Nakamura, Kiyoto; Fujisaki, Takashi, Test carrier.
  41. Leedy, Glenn J, Three dimension structure memory.
  42. Leedy, Glenn J, Three dimensional memory structure.
  43. Leedy, Glenn J, Three dimensional memory structure.
  44. Leedy, Glenn J, Three dimensional structure memory.
  45. Leedy, Glenn J, Three dimensional structure memory.
  46. Leedy, Glenn J, Three dimensional structure memory.
  47. Leedy, Glenn J., Three dimensional structure memory.
  48. Leedy, Glenn J., Three dimensional structure memory.
  49. Leedy, Glenn J., Three dimensional structure memory.
  50. Leedy, Glenn J., Three dimensional structure memory.
  51. Leedy, Glenn J., Three dimensional structure memory.
  52. Leedy, Glenn J., Three dimensional structure memory.
  53. Leedy, Glenn J., Three dimensional structure memory.
  54. Leedy, Glenn J, Vertical system integration.
  55. Leedy, Glenn J, Vertical system integration.
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