|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||382/34 ; 364/72805 ; 365/230 ; 382/42|
|발명자 / 주소|
|출원인 / 주소|
|인용정보||피인용 횟수 : 40 인용 특허 : 8|
A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating ad...
A controller for a plurality of image correlation circuits, each correlation circuit having a memory for storing a portion of a source image to be correlated with a pattern, each said memory having a portion of its address inputs coupled to a common address bus, comprising: means for generation correlator addresses by adding a predetermined increment to said correlator address while controlling the most significant bit of said correlator addresses, said correlator addresses corresponding to source image addresses with at least one of the most significant...