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Semiconductor package

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0643530 (1984-08-23)
발명자 / 주소
  • Butt Sheldon H. (Godfrey IL)
출원인 / 주소
  • Olin Corporation (New Haven CT 02)
인용정보 피인용 횟수 : 53  인용 특허 : 16

초록

A semiconductor package for mounting a chip is disclosed. The package includes a first metal or metal alloy component having a first thin refractory oxide layer on a first surface. The chip is bonded to the first component. A skirt extends from the first component for strengthening the first compone

대표청구항

A semiconductor package adapted for an integrated circuit chip comprising: a substrate member, said substrate member being a material from the group consisting of metal and metal alloy; a cover member being mounted upon said substrate member to provide a hollow enclosure for receiving said chip, sai

이 특허에 인용된 특허 (16)

  1. Butt Sheldon H. (Godfrey IL), Casing for an electrical component having improved strength and heat transfer characteristics.
  2. Andrews Daniel M. (San Marcos CA) Merlina Joseph F. (Harrisburg PA) Redmond John P. (Mechanicsburg PA) Scheingold William S. (Palmyra PA) Ulbrich George (Harrisburg PA), Chip carrier.
  3. Morris ; Sr. James B. (San Jose CA), Combined semiconductor device and printed circuit board assembly.
  4. Butt Sheldon H. (Godfrey IL), Composites of glass-ceramic to metal seals and method of making the same.
  5. Burgyan ; Stephan J., Composites of glass-ceramic-to-metal, seals and method of making same.
  6. Spinelli, Thomas S.; Manns, William G.; Weirauch, Donald F., Electronic circuit interconnection system.
  7. Sherman Charles J. (Westminster CO), Electronic device packaging arrangement.
  8. Popplewell James M. (Guilford CT), Glass or ceramic-to-metal composites or seals involving iron base alloys.
  9. Hascoe ; Norman, Hermetically sealed container for semiconductor and other electronic device s.
  10. Cossutta ; Giuseppe ; Cellai ; Marino, Molded body incorporating heat dissipator.
  11. Barnes Norman S. (Whitesboro NY) Mogle Rodman A. (Clinton NY), Molybdenum substrate thick film circuit.
  12. Takami Akio (Nagoya JPX) Kondo Kazuo (Nagoya JPX) Tanaka Kazutoshi (Nagoya JPX), Seal structure of ceramics and low expansion metallic material.
  13. Hutchison Robert V. (Oceanside CA), Semiconductor device package having lead frame structure with integral spring contacts.
  14. Narita Kazutoyo (Hitachi JA) Sakaue Tadashi (Hitachi JA) Niino Yuzi (Hitachi JA), Semiconductor device with composite metal heat-radiating plate onto which semiconductor element is soldered.
  15. Schneider Stanley (Newport Beach CA), Solid state relay having U-shaped conductive heat sink frame.
  16. Lifshin, Eric; Cargioli, Joseph D.; Schroder, Stephen J.; Wong, Joe, Transfer lamination of copper thin sheets and films, method and product.

이 특허를 인용한 특허 (53)

  1. Mahulikar Deepak (Madison CT) Sagiv Efraim (Meriden CT) Parthasarathi Arvind (North Branford CT) Jalota Satish (Wallingford CT) Brock Andrew J. (Cheshire CT) Holmes Michael A. (Ripon CA) Schlater Jef, Anodized aluminum substrate having increased breakdown voltage.
  2. Schuurman Derek C.,CAX ; Lankin Robert G.,CAX ; Hellinga Richard J.,CAX, Bus bar heat sink.
  3. Dibene ; II Joseph T. ; Wang Gang ; Muller P. Keith, Centralized cooling interconnect for electronic packages.
  4. Martter, Robert H.; Sundberg, Craig C.; Giardina, Richard N.; Fetscher, Brian S.; Deutschlander, G. James, Circuit board.
  5. Achyuta Achari ; Andrew Zachary Glovatsky ; Robert Edward Belke ; Brenda Joyce Nation ; Delin Li ; Lakhi N. Goenka ; Robert Joseph Gordon ; Thomas Bernd Krautheim, Circuit board and a method for making the same.
  6. Chen Shiaw-Jong Steve ; Hooey Roger J. ; Truong Thang D., Circuit board apparatus.
  7. Fazelpour, Siamak; Hashemi, Hassan S., Controlled impedance leads in a leadframe for high frequency applications.
  8. Akram, Salman, Copper interconnect.
  9. Akram,Salman, Copper interconnect.
  10. Akram,Salman, Copper interconnect.
  11. Akram,Salman, Copper interconnect for semiconductor device.
  12. Will Specks DE; Nils Bossemeyer DE; Mervi Paulasto DE, Electronic device package, and method.
  13. Ferguson, John Thomas, Focused LED headlamp with iris assembly.
  14. Jech David E. ; Frazier Jordan P. ; Sworden Richard H. ; Sepulveda Juan L., Functionally graded metal substrates and process for making same.
  15. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  16. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  17. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  18. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
  19. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
  20. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip in wafer form.
  21. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
  22. Chu George D. (Newark CA), High performance plastic encapsulated package for integrated circuit die.
  23. Suzaki Hidefumi,JPX, Integrated dielectric substrate.
  24. Mahulikar Deepak (Meriden CT) Braden Jeffrey S. (Milpitas CA) Noe Stephen P. (Stratford CT), Metal electronic package having improved resistance to electromagnetic interference.
  25. Deeney,Jeffrey L.; Dutson,Joseph D.; Luebs,Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using an external support.
  26. Deeney, Jeffrey L.; Dutson, Joseph D.; Luebs, Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using external support.
  27. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
  28. Tower Steven A. ; Mravic Brian, Method for making a ceramic to metal hermetic seal.
  29. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  30. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  31. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  32. Zhan, Peng-Han, Method of interrupt control and electronic system using the same.
  33. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  34. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  35. Hsieh, Ming-Hsun, Motion sensing device and packaging method thereof.
  36. Hsieh, Ming-Hsun, Motion sensor and packaging method thereof.
  37. Lin, Chih Hsiung; Chang, Nai Shung, Multi-package module and electronic device using the same.
  38. Lin, Chih-Hsiung; Chang, Nai-Shung, Multi-package module and electronic device using the same.
  39. Tower Steven A. ; Mravic Brian, Optical component package with a hermetic seal.
  40. Usui, Hirotoshi, Package-in-substrate, semiconductor device and module.
  41. Silverman, Lawrence H., Pocket mounted chip having microstrip line.
  42. Nakamura Hiroshi,JPX ; Nakajima Yuji,JPX, Portable computer having a circuit board including a heat-generating IC chip and a metal frame supporting the circuit bo.
  43. Kawase, Tatsuya; Miyamoto, Noboru; Ishihara, Mikio, Semiconductor device.
  44. Akram, Salman, Semiconductor device having copper interconnect for bonding.
  45. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  46. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  47. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  48. Dieter Ferling DE; Anca Gutu-Nelle DE, Submount, electronic assembly and process for producing the same.
  49. Su,Chao Yuan; Huang,Chen Der; Tsao,Pei Haw; Lin,Chuen Jye, Substrate design to improve chip package reliability.
  50. Haley Kevin J. ; Delaplane Niel C. ; Mahajan Ravindranath V. ; Starkston Robert ; Gealer Charles A. ; Krauskopf Joseph C., Thermal interface thickness control for a microprocessor.
  51. Dalton, James; Single, Peter; Money, David, Virtual wire assembly having hermetic feedthroughs.
  52. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
  53. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
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