초록 ▼

A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. Th

A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.

대표청구항 ▼

A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second pluralit

A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits from which at least one digit of error may be detected and corrected in the block of data, a plurality of read/write memory units, which store the digits of said blocks of data and associated error correction codes generated by said error correction code generation circuit and read said digits, at least some of the different digits of each code and its associated data block being stored in different memory units, at least one spare read/write memory unit that is similar in operation to an individual read/write memory unit of said plurality of read/write memory units, means for generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating means operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits, and means for accessing the spare read/write memory unit to store therein said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.