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Multiple function data processor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0234124 (1988-08-19)
발명자 / 주소
  • Judd James E. (Maple Shade NJ)
출원인 / 주소
  • General Electric Company (Moorestown NJ 02)
인용정보 피인용 횟수 : 89  인용 특허 : 7

초록

A data processor includes a reconfigurable arithmetic logic unit (ALU), which includes three ALU portions. One ALU portion includes two 16-bit input ports and a 16-bit output port. The other two ALU portions each include two 8-bit input ports and an 8-bit output port. A reconfigurable 16-bit registe

대표청구항

An arrangement for processing 2N-bit data produced at first and second N-bit source ports, which data is configurable in the form of a 2N-bit word or two N-bit words or a word including 3N/2-bit mantissa with N/2-bit exponent, comprising: an N-bit register file including first and second N-bit input

이 특허에 인용된 특허 (7)

  1. Lamb Kenneth J. (Plympton GB2), Arithmetic logic and shift device.
  2. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  3. Vaughn Herchel A. (Austin TX), Arithmetic logic unit utilizing strobed gates.
  4. Yokoyama Yasushi (Tokyo JPX), Arithmetic unit with simple overflow detection system.
  5. Kuroda Ichiro (Tokyo JPX) Nishitani Takao (Tokyo JPX) Tanaka Hideo (Tokyo JPX) Kawakami Yuichi (Tokyo JPX), Double precision multiplier.
  6. Imel Michael T. (Beaverton OR) Lai Konrad (Aloha OR) Myers Glenford J. (Aloha OR) Steck Randy (Aloha OR) Valerio James (Portland OR), Mixed-precision floating point operations from a single instruction opcode.
  7. Yokomizo Goichi (C406 ; 2-32 ; Koyasucho Hachioji-shi ; Tokyo JPX) Torii Shunichi (4-26-16-301 ; Honcho Kichijoji ; Musashino-shi ; Tokyo JPX) Hamada Hozumi (2-63-7 Kikunodai ; Chofu-shi ; Tokyo JPX), Operation unit for floating point data with variable exponent-part length.

이 특허를 인용한 특허 (89)

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  4. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  5. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  13. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
  14. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  15. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
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  27. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  28. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  29. Guttag Karl M. ; Read Christopher J. ; Balmer Keith,GBX, Long instruction word controlling plural independent processor operations.
  30. Baum Allen J. (Palo Alto CA), Method and apparatus for multi-gauge computation.
  31. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  32. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  33. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  34. Vorbach, Martin, Method for debugging reconfigurable architectures.
  35. Vorbach, Martin, Method for debugging reconfigurable architectures.
  36. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  37. Vorbach,Martin, Method for debugging reconfigurable architectures.
  38. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
  39. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
  40. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  41. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  42. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
  43. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  44. May,Frank; N?ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
  45. Na Ra Won KR; Sung Goo Park KR, Method for transmitting data between a microprocessor and an external memory module by using combined serial/parallel process.
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  47. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  48. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
  49. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
  50. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  61. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
  62. Vorbach, Martin, Methods and devices for treating and/or processing data.
  63. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  64. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  70. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  71. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  72. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  73. Hanai, Takashi; Kawano, Tetsuo, Reconfigurable circuit.
  74. Vorbach, Martin, Reconfigurable elements.
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  76. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  77. Vorbach,Martin; M?nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
  78. Vorbach, Martin, Reconfigurable sequencer structure.
  79. Vorbach, Martin, Reconfigurable sequencer structure.
  80. Vorbach, Martin, Reconfigurable sequencer structure.
  81. Vorbach, Martin, Reconfigurable sequencer structure.
  82. Vorbach,Martin, Reconfigurable sequencer structure.
  83. Vorbach, Martin; Bretz, Daniel, Router.
  84. Vorbach,Martin; Bretz,Daniel, Router.
  85. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.
  86. Vorbach,Martin; M?nch,Robert, Run-time reconfiguration method for programmable units.
  87. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  88. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  89. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
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