IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0234124
(1988-08-19)
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발명자
/ 주소 |
- Judd James E. (Maple Shade NJ)
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출원인 / 주소 |
- General Electric Company (Moorestown NJ 02)
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인용정보 |
피인용 횟수 :
89 인용 특허 :
7 |
초록
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A data processor includes a reconfigurable arithmetic logic unit (ALU), which includes three ALU portions. One ALU portion includes two 16-bit input ports and a 16-bit output port. The other two ALU portions each include two 8-bit input ports and an 8-bit output port. A reconfigurable 16-bit registe
A data processor includes a reconfigurable arithmetic logic unit (ALU), which includes three ALU portions. One ALU portion includes two 16-bit input ports and a 16-bit output port. The other two ALU portions each include two 8-bit input ports and an 8-bit output port. A reconfigurable 16-bit register file is coupled to the inputs of the ALU portions. Switches couple carry output terminals of the second and third ALU portions to carry input terminals of the first and second ALU portions, respectively. With both switches conductive, a 32-bit ALU is formed from the three portions. With a first switch open, two independent 16-bit ALUs are formed. With the second switch open and the first closed, 24-bit mantissa, 8 bit exponent floating-point processing can be done by independent ALUs. The output of the first ALU portion loops back by a first multiplexer to a first 16-bit input of a register, and the two 8-bit outputs of the second and third ALU portions loop back by a second multiplexer to a second 16-bit input of the register. The register output couples words to be processed to the ALU portions.
대표청구항
▼
An arrangement for processing 2N-bit data produced at first and second N-bit source ports, which data is configurable in the form of a 2N-bit word or two N-bit words or a word including 3N/2-bit mantissa with N/2-bit exponent, comprising: an N-bit register file including first and second N-bit input
An arrangement for processing 2N-bit data produced at first and second N-bit source ports, which data is configurable in the form of a 2N-bit word or two N-bit words or a word including 3N/2-bit mantissa with N/2-bit exponent, comprising: an N-bit register file including first and second N-bit input ports and first, second, third, fourth, fifth and sixth output ports, said first and second output ports having N bits, said third and fourth output ports each having N/2 bits which together constitute one N-bit output port, with said third output port representing the most significant of said N bits, and said fourth output port representing the remaining bits of lesser significance, said fifth and sixth output ports each having N/2 bits, which together constitute one N-bit output port, with said fifth output port representing the most significant bits, and said sixth output port representing the remaining bits of lesser significance; a dynamically reconfigurable arithmetic logic unit including first and second input ports coupled to a first portion of said arithmetic logic unit, said first and second input ports of said first portion of said arithmetic logic unit each having N bits and being coupled to said first and second output ports of said register file, respectively, said first portion of said arithmetic logic unit further including a carry input terminal and an N-bit output port, said reconfigurable arithmetic logic unit further including third and fourth input ports coupled to a second portion of said arithmetic logic unit, said second portion of said arithmetic logic unit further including a carry input terminal, a carry output terminal, and an N/2 bit output port, said third input port of said arithmetic logic unit having N/2 bits and being coupled to said third output port of said register file, said fourth input port of said arithmetic logic unit having N/2 bits and being coupled to said fifth output port of said register file, said reconfigurable arithmetic logic unit further including fifth and sixth input ports coupled to a third portion of said arithmetic logic unit, said third portion of said arithmetic logic unit further including a carry output terminal and an N/2 bit output port, said fifth input port of said arithmetic logic unit having N/2 bits and being coupled to said fourth output port of said register file, and said sixth input port of said arithmetic logic unit having N/2 bits and being coupled to said sixth output port of said register file, said reconfigurable arithmetic logic unit further including first and second controllable switch means, said first switch means including a controllable path coupled to said carry output terminal of said second portion of said arithmetic logic unit and to said carry input terminal of said first portion of said arithmetic logic unit, said second switch means including a controllable path coupled to said carry output terminal of said third portion of said arithmetic logic unit and to said carry input terminal of said second portion of said arithmetic logic unit, said first and second switch means each further including control input terminals; coupling means coupled to said first and second N-bit input port of said register file and adapted to be coupled to said first and second N-bit source ports for coupling data from said first and second source ports to said first and second input ports of said register file, respectively; switch control means coupled to said first and second switch means for controlling said switch means in first, second and third operating modes, said first operating mode having said first and second switch means closed for thereby operating said first, second and third portions of said arithmetic logic unit together as a 2N-bit arithmetic logic unit, said second operating mode having said first switch means open and said second switch means closed for thereby operating said first portion of said arithmetic logic unit independently and for operating said second and third portions of said arithmetic logic unit together as an N-bit portion, said third operating mode having said first switch means closed and said second switch means open for thereby forming a 3N/2 bit portion of said arithmetic logic unit including said first and second portions of said arithmetic logic unit together with a separate N/2 bit portion including said third portion of said arithmetic logic unit.
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