$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Clamping circuit for a PLL tuning system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04B-011/16
출원번호 US-0061757 (1987-06-15)
발명자 / 주소
  • Marik Charles J. (Richmond IL) Ecklund Lawrence (Wheaton IL)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 46  인용 특허 : 8

초록

An AM Stereo receiver is described which includes an AGC having an output which indicates whether the received signal has significantly decreased in level and having a clamping circuit for controlling the voltage at the input of a VCO. The clamping circuit is further defined as having a window detec

대표청구항

In a receiver which includes sensor means for detecting a decrease in the level of a received signal, a clamping circuit for controlling the voltage coupled to the input of a VCO, comprising: window detection means for sensing a change responsive to the frequency of said received signal in the volta

이 특허에 인용된 특허 (8)

  1. Moeller Charles P. (Del Mar CA), Cyclotron resonance maser amplifier and waveguide window.
  2. Rogers Terrence E. (Portsmouth VA), Digital automatic frequency control with tracking.
  3. Krinock Jerome V. (Owensboro KY), Fast acquisition circuit for synchronous digital receiver operating in wideband noise.
  4. Morita Hiroyuki (Kumagaya JPX), Frequency converting circuit.
  5. Ishida Koji (Tokyo JPX), IF Signal processing circuit in a receiver.
  6. Takahashi Kozo (Higashi-Kurume JPX), Method for diversity reception and apparatus therefor.
  7. Kimura Robert K. (Gardena CA) Itri Benedict A. (Torrance CA), PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction.
  8. Ikeguchi Shigehiko (Oora JPX) Tanaka Kouzi (Oora JPX), Tuning control apparatus of receiver.

이 특허를 인용한 특허 (46)

  1. Wu,Stephen; Ibrahim,Brima; Rofougaran,Ahmadreza, Adaptive radio transceiver with polyphase calibration.
  2. Yang Jae Mo,KRX, Automatic frequency control method.
  3. Ward, Christopher M.; Vorenkamp, Pieter, Differential crystal oscillator.
  4. Buhler, Otto; Waynik, Jeffrey M.; Dillinger, Forest K., Dropout resistant phase-locked loop.
  5. Woo,Agnes Neves; Chen,Chun Ying, ESD configuration for low parasitic capacitance I/O.
  6. Woo, Agnes Neves, ESD protection for high voltage applications.
  7. Woo,Agnes Neves, ESD protection for high voltage applications.
  8. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank; Ward, Christopher M.; Duncan, Ralph; Kwan, Tom W.; Chang, James Y. C.; Khorramabadi, Haideh, Fully integrated tuner architecture.
  9. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank; Ward, Christopher M.; Duncan, Ralph; Kwan, Tom W.; Chang, James Y. C.; Khorramabadi, Haideh, Fully integrated tuner architecture.
  10. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank; Ward,Christopher M.; Duncan,Ralph; Kwan,Tom W.; Chang,James Y. C.; Khorramabadi,Haideh, Fully integrated tuner architecture.
  11. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank; Ward,Christopher M.; Duncan,Ralph; Kwan,Tom W.; Chang,James Y. C.; Khorramabadi,Haideh, Fully integrated tuner architecture.
  12. Duncan, Ralph; Kwan, Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
  13. Duncan,Ralph; Kwan,Tom W., Integrated VCO having an improved tuning range over process and temperature variations.
  14. Chang, James Y. C., Integrated spiral inductor.
  15. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  16. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  17. Bult, Klaas; Gomez, Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  18. Bult,Klaas; Gomez,Ramon A., Integrated switchless programmable attenuator and low noise amplifier.
  19. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
  20. Behzad, Arya R., Large gain range, high linearity, low noise MOS VGA.
  21. Behzad,Arya R., Large gain range, high linearity, low noise MOS VGA.
  22. Chang, James Y. C., Multi-track integrated circuit inductor.
  23. Chang, James Y. C., Multi-track integrated spiral inductor.
  24. Ward, Christopher M.; Vorenkamp, Pieter, Phase locked loop.
  25. Agnes N. Woo ; Kenneth R. Kindsfater ; Fang Lu, System and method for ESD Protection.
  26. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  27. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  28. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  29. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  30. Woo, Agnes N.; Kindsfater, Kenneth R.; Lu, Fang, System and method for ESD protection.
  31. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
  32. Woo,Agnes N.; Kindsfater,Kenneth R.; Lu,Fang, System and method for ESD protection.
  33. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for coarse/fine PLL adjustment.
  34. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank, System and method for coarse/fine PLL adjustment.
  35. Khorramabadi, Haideh, System and method for linearizing a CMOS differential pair.
  36. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
  37. Khorramabadi,Haideh, System and method for linearizing a CMOS differential pair.
  38. Ralph Duncan ; Tom W. Kwan, System and method for narrow band PLL tuning.
  39. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  40. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  41. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, System and method for on-chip filter tuning.
  42. Carr,Frank; Vorenkamp,Pieter, System and method for providing a low power receiver design.
  43. Frank Carr ; Pieter Vorenkamp, System and method for providing a low power receiver design.
  44. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, Temperature compensation for internal inductor resistance.
  45. Vorenkamp, Pieter; Bult, Klaas; Carr, Frank, Temperature compensation for internal inductor resistance.
  46. Vorenkamp,Pieter; Bult,Klaas; Carr,Frank, Temperature compensation for internal inductor resistance.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로