초록 ▼

The essence of the invention is a socalled “data bit variable spacer generator”, block 79, which contributes to the generation of a control output “c”from a combinatory logic circuit group 78. The logic level of “c”determines whether a clear data bit from the parity flip flop FF6 is to be sent out o

The essence of the invention is a socalled “data bit variable spacer generator”, block 79, which contributes to the generation of a control output “c”from a combinatory logic circuit group 78. The logic level of “c”determines whether a clear data bit from the parity flip flop FF6 is to be sent out or a random bit from block RMG. The ‘variable data bit generator’is controlled by a number of parallel bit outputs from registers SH1 and SH2 which hold an encryption key after being conditioned by other logic inputs derived from key parity flip flops (FF1 and FF2) and clear data bit levels from block 81. Registers SH1 and SH2 shift and recirculate when the ‘c’output is high. Similar principles are used when data are decrypted. The circuit is suitable for integration with other functions on a single substrate chip.

대표청구항 ▼

An electronic money purse system using encrypted fund transfer signals comprising at least one central computer station, a variety of terminals at different locations and a multiplicity of electronically operated value storage carriers the circuit logic of which includes means for encrypting the dat

An electronic money purse system using encrypted fund transfer signals comprising at least one central computer station, a variety of terminals at different locations and a multiplicity of electronically operated value storage carriers the circuit logic of which includes means for encrypting the data communicated to a terminal, the encrypting means including at least one cipher key register, a random data generator, and additional means for varying the spacing of data bits in a serial mixture of random data and transaction data wherein the data bit spacing is determined in dependence on the logic levels of selected bit positions of the cipher key register as well as on the sequentially appearing data to be transmitted from or being received in the said storage carrier.