$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Dual-rail processor with error checking at single rail interfaces 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/20
출원번호 US-0093584 (1987-09-04)
발명자 / 주소
  • Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA)
출원인 / 주소
  • Digital Equipment Corporation (Maynard MA 02)
인용정보 피인용 횟수 : 61  인용 특허 : 22

초록

A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared re

대표청구항

A dual processor computer system with error checking capability comprising: a first processing system for executing a series of instructions including output instructions containing data to be written into a designated system element; a second processing system for executing said series of instructi

이 특허에 인용된 특허 (22)

  1. De Bimal B. (Naperville IL) Gierut Lawrence G. (Lockport IL) Krakau Herbert B. (Elmhurst IL) Naik Kirit (Hanover Park IL) Tan-Atichat Eddie (Westmont IL), Automatic fault recovery system for a multiple processor telecommunications switching control.
  2. Censier Lucien (Conflans FR) Recoque Alice Maria (Chatenet Malabry FR), Bi-processor data handling system including automatic control of exchanges with external equipment and automatically act.
  3. Reid Robert (Dunstable MA), Central processing apparatus for fault-tolerant computing.
  4. Wolff Kenneth T. (Medway MA) Samson Joseph E. (Dover MA) Baty Kurt F. (Medway MA), Computer peripheral control apparatus.
  5. Joby Michael J. (Solihull GB2), Digital computing apparatus particularly for controlling a gas turbine engine.
  6. Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medway MA) Reid Robert (Dunstable MA) Hendrie Gardner C. (Marlboro MA) Falkoff Daniel M. (Natick MA) Dynneson Ronald E. (Brighton MA) Clemson Daniel M. (, Digital data processor with high reliability.
  7. Strelow Horst (Cremlingen DEX), Dual-channel data processing system for railroad safety purposes.
  8. Sakata Kazuhiro (Katsuta JPX) Yuminaka Takeo (Katsuta JPX) Nakazato Masao (Katsuta JPX) Yoneda Kenji (Katsuta JPX) Kuzunuki Soshiro (Hitachi JPX) Katayama Yasunori (Hitachi JPX), Elevator control system.
  9. Whiteside Arliss E. (Royal Oak MI) Freedman Morris D. (Southfield MI) Rothschild Alexander M. (Ann Arbor MI) Tasar mr (Harvard MA), Fault-tolerant multi-computer system.
  10. Beier Harley A. (Morgan Hill CA) Fukumoto Takeshi (Yokohama CA JPX) Scofield Harrison (Morgan Hill CA) Watts Vern L. (Los Gatos CA), Improving availability of a restartable staged storage data base system that uses logging facilities.
  11. Woods ; John M. ; Porter ; Marion G. ; Mills ; Donald V. ; Weller ; III ; Edward F. ; Patterson ; Garvin Wesley ; Monahan ; Earnest M., Input/output processing system utilizing locked processors.
  12. Plyler Robert G. (Vienna OH) Seagreaves George F. (Warren OH) Suverison Lyle B. (Fowler OH), Locking shield for electrical terminal.
  13. MacDougall James R. (Plano TX) Richter David L. (Plano TX), Memory unit with pipelined cycle of operations.
  14. Kawase Buntaro (Tokyo JA) Kojima Iwao (Yokohama JA) Kasai Juichi (Fujisawa JA) Kawasaki Keiji (Tokyo JA), Method of removing mercury vapor from gases contaminated therewith.
  15. Katzman James A. (San Jose CA) Bartlett Joel F. (Palo Alto CA) Bixler Richard M. (Sunnyvale CA) Davidow William H. (Atherton CA) Despotakis John A. (Pleasanton CA) Graziano Peter J. (Los Altos CA) Gr, Multiprocessor system.
  16. Piras Giancarlo (Milan ITX), Parallel multiprocessing system for an industrial plant.
  17. Keiles Yoel (Havertown PA), Process control system with backup process controller.
  18. Richter David L. (Plano TX), Processing system with dual buses.
  19. Long James R. (Huntsville AL) Harrill Roy L. (Walton Beach FL), Remote multiplexer terminal with redundant central processor units.
  20. Stiffler, Jack J.; Budwey, Michael J.; Nolan, Jr., James M., Self-checking computer circuitry.
  21. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  22. Davis Guy E. (Martinez CA), System for manually or automatically transferring control between computers without power generation disturbance in an e.

이 특허를 인용한 특허 (61)

  1. Sonnier David Paul ; Baker William Edward ; Bunton William Patterson ; Krause John C. ; Porter Kenneth H. ; Watson William Joel ; Zalzala Linda Ellen, Apparatus for detecting divergence between a pair of duplexed, synchronized processor elements.
  2. Vogt, Pete D., Combined command and data code.
  3. Ellis, Frampton E., Computer or microchip controlled by a firewall-protected master controlling microprocessor and firmware.
  4. Ellis, Frampton E., Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller.
  5. Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.
  6. Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.
  7. Ellis, Frampton E., Computer or microchip with a secure system bios having a separate private network connection to a separate private network.
  8. Ellis, Frampton E., Computer or microchip with an internal hardware firewall and a master controlling device.
  9. Ellis, Frampton E., Computer or microchip with its system bios protected by one or more internal hardware firewalls.
  10. Ellis, Frampton E., Computer with at least one faraday cage and internal flexibility sipes.
  11. Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
  12. Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.
  13. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewall.
  14. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewalls.
  15. Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
  16. Ellis, III, Frampton Erroll, Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
  17. Ellis, Frampton E., Computers including an undiced semiconductor wafer with Faraday Cages and internal flexibility sipes.
  18. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.
  19. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.
  20. Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.
  21. Dearth Glenn (Groton MA) Bissett Thomas D. (Northboro MA), DMA controller for memory scrubbing.
  22. Zizzi,Stephen, Encrypting file system.
  23. Gallagher,James R.; Hua,Binh K.; Kodukula,Sivarama K.; Ratcliff,Bruce Henry, End-to-end data integrity protection for PCI-Express based input/output adapter.
  24. Sampson Neil L. ; Gray Scott L. ; Walker Gary, Error detection and correction for data stored across multiple byte-wide memory devices.
  25. Ohguro Hiroshi,JPX ; Ikeda Koichi,JPX ; Nishiyama Takaaki,JPX ; Iwamoto Hiroshi,JPX ; Kurosawa Kenichi,JPX ; Nakamikawa Tetsuaki,JPX ; Morioka Michio,JPX, Fault recovering system provided in highly reliable computer system having duplicated processors.
  26. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  27. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  28. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik, Fault resilient/fault tolerant computing.
  29. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  30. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  31. Thomas D. Bissett ; Paul A. Leveille ; Erik Muench, Fault resilient/fault tolerant computing.
  32. Oguro Hiroshi,JPX ; Yamaguchi Shinichiro,JPX ; Miyazaki Yoshihiro,JPX ; Takaya Soichi,JPX ; Hiramatsu Masataka,JPX ; Akeura Nobuo,JPX, Fault-tolerant computer system.
  33. Jenkins,Steven Kenneth; Leavens,Ross Boyd; Likovich, Jr.,Robert Brian; Queen,Wesley Erich; Siegel,Michael Steven, Flow lookahead in an ordered semaphore management subsystem.
  34. Ellis, Frampton E., Footwear sole sections including bladders with internal flexibility sipes therebetween and an attachment between sipe surfaces.
  35. Ellis, Frampton E., Global network computers.
  36. Horst Robert W., Logical, fail-functional, dual central processor units formed from three processor units.
  37. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik ; Tremblay Glenn A., Loosely-coupled, synchronized execution.
  38. Rajamani, Ramasubramanian, Memory buffers for merging local data from memory modules.
  39. Heddes,Marco; Jenkins,Steven Kenneth; Leavens,Ross Boyd; Likovich, Jr.,Robert Brian, Method and apparatus for locking multiple semaphores.
  40. Ellis, Frampton E., Microchip with faraday cages and internal flexibility sipes.
  41. Ellis, Frampton E, Microchips with an internal hardware firewall.
  42. Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.
  43. Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.
  44. Ellis, Frampton E., Microchips with multiple internal hardware-based firewalls and dies.
  45. Calvignac,Jean Louis; Davis,Gordon Taylor; Heddes,Marco; Jenkins,Steven Kenneth; Leavens,Ross Boyd; Likovich, Jr.,Robert Brian, Ordered semaphore management subsystem.
  46. V?th,Joachim, Peripheral component with high error protection for stored programmable controls.
  47. Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.
  48. Jackson, Timothy E., Processing packets in an aircraft network data processing system.
  49. Mohat William D., Processor independent error checking arrangement.
  50. Micka William F. (Tucson AZ) Mikkelsen Claus W. (San Jose CA) Shomler Robert W. (Morgan Hill CA) Wone May N. (San Jose CA), Remote copy secondary data copy validation-audit function.
  51. Horst Robert W. ; Garcia David J. ; Bunton William Patterson ; Bruckert William F. ; Fowler Daniel L. ; Jones ; Jr. Curtis Willard ; Sonnier David Paul ; Watson William Joel ; Williams Frank A., Self-checked, lock step processor pairs.
  52. Vigil Peter J. ; Lederer Louis S. ; Blomgren James S., Self-testing multi-processor die with internal compare points.
  53. Davis,Gordon Taylor; Heddes,Marco; Jenkins,Steven Kenneth; Leavens,Ross Boyd; Likovich, Jr.,Robert Brian, Semaphore management subsystem for use with multi-thread processor systems.
  54. Pignol,Michel, Software system tolerating transient errors and control process in such a system.
  55. Ellis, Frampton E., Surgically implantable device enclosed in two bladders configured to slide relative to each other and including a faraday cage.
  56. Mende, Jr., Robert G.; Vasa, Mayank V., System and method for maintaining and recovering data consistency across multiple instances of a database.
  57. Mende, Jr., Robert G.; Vasa, Mayank V., System and method for maintaining and recovering data consistency across multiple pages.
  58. Mende, Jr.,Robert G., System and method for maintaining and recovering data consistency in a data base page.
  59. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for preserving the state of a device across a reset event.
  60. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for reducing the effects of hardware faults in a computer system employing multiple central processin.
  61. Beardsley Brent Cameron (Tucson AZ) Knowlden Ronald Robert (Tucson AZ) Spear Gail Andrea (Tucson AZ), Use of configuration registers to control access to multiple caches and nonvolatile stores.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로