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A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or al

A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or alignment to fill a complete entry in a line in the cache, the bus master automatically transfers additional operands adjacent in the memory to the requested operand sufficient to fill that entry.

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In a data processing system having a bus master for controlling transferring a predetermined operand from a system memory into an entry in a line of a cache memory via a data bus, wherein the predetermined operand or a portion thereof provided by the system memory during an initial bus cycle is insu

In a data processing system having a bus master for controlling transferring a predetermined operand from a system memory into an entry in a line of a cache memory via a data bus, wherein the predetermined operand or a portion thereof provided by the system memory during an initial bus cycle is insufficient in size or alignment to fill said entry, the bus master comprising: a data translator having a programmable logic device for indicating at least a portion of an address where the predetermined operand is to be written in the cache memory, for receiving a first size signal indicating bit size of the predetermined operand, and for receiving a second size signal indicating data port size between the bus master and system memory, and in response thereto, said programmable logic device providing an output control signal having a predetermined value corresponding to said input data and for use by the system, said output control signal indicating that an immediately subsequent bus cycle is an additional bus cycle line of the cache memory and which controls the subsequent filling of the entry by coupling data from the system memory which is required to fill the entry in the cache line, said data translator also detecting completion of the filling of the entry and providing an entry fill cycle complete signal in response thereto, said entry fill cycle complete signal being used by the system to set valid a predetermined valid entry bit in said cache line.