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Interface of non-fault tolerant components to fault tolerant system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/16
출원번호 US-0093539 (1987-09-04)
발명자 / 주소
  • Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Norcross Mitchell O. (Framingham MA) Ward Kenneth A. (Marlboro MA)
출원인 / 주소
  • Digital Equipment Corporation (Maynard MA 02)
인용정보 피인용 횟수 : 19  인용 특허 : 22

초록

A fault tolerant computer system includes a fault tolerant data processing module which has means for detecting and correcting errors in the operation of the data processing module to maintain a high degree of data integrity. Data transmission control devices control the transmission of all data to

대표청구항

A fault tolerant computer system comprising: a fault tolerant data processing module including means for detecting and correcting errors in the operation of said data processing module to maintain a high degree of data integrity, data transmission control means for controlling the transmission of al

이 특허에 인용된 특허 (22)

  1. De Bimal B. (Naperville IL) Gierut Lawrence G. (Lockport IL) Krakau Herbert B. (Elmhurst IL) Naik Kirit (Hanover Park IL) Tan-Atichat Eddie (Westmont IL), Automatic fault recovery system for a multiple processor telecommunications switching control.
  2. Censier Lucien (Conflans FR) Recoque Alice Maria (Chatenet Malabry FR), Bi-processor data handling system including automatic control of exchanges with external equipment and automatically act.
  3. Reid Robert (Dunstable MA), Central processing apparatus for fault-tolerant computing.
  4. Wolff Kenneth T. (Medway MA) Samson Joseph E. (Dover MA) Baty Kurt F. (Medway MA), Computer peripheral control apparatus.
  5. Joby Michael J. (Solihull GB2), Digital computing apparatus particularly for controlling a gas turbine engine.
  6. Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medway MA) Reid Robert (Dunstable MA) Hendrie Gardner C. (Marlboro MA) Falkoff Daniel M. (Natick MA) Dynneson Ronald E. (Brighton MA) Clemson Daniel M. (, Digital data processor with high reliability.
  7. Strelow Horst (Cremlingen DEX), Dual-channel data processing system for railroad safety purposes.
  8. Eki Yurio (Hitachi JPX) Tennichi Yasuhiro (Hitachi JPX) Honda Naganobu (Hitachi JPX), Electro-hydraulic governor employing duplex digital controller system.
  9. Sakata Kazuhiro (Katsuta JPX) Yuminaka Takeo (Katsuta JPX) Nakazato Masao (Katsuta JPX) Yoneda Kenji (Katsuta JPX) Kuzunuki Soshiro (Hitachi JPX) Katayama Yasunori (Hitachi JPX), Elevator control system.
  10. Whiteside Arliss E. (Royal Oak MI) Freedman Morris D. (Southfield MI) Rothschild Alexander M. (Ann Arbor MI) Tasar mr (Harvard MA), Fault-tolerant multi-computer system.
  11. Beier Harley A. (Morgan Hill CA) Fukumoto Takeshi (Yokohama CA JPX) Scofield Harrison (Morgan Hill CA) Watts Vern L. (Los Gatos CA), Improving availability of a restartable staged storage data base system that uses logging facilities.
  12. MacDougall James R. (Plano TX) Richter David L. (Plano TX), Memory unit with pipelined cycle of operations.
  13. Erlandson Paul M. (Palos Park IL) Szatkowski Richard R. (Western Springs IL), Method for high speed sinter molding.
  14. Kawase Buntaro (Tokyo JA) Kojima Iwao (Yokohama JA) Kasai Juichi (Fujisawa JA) Kawasaki Keiji (Tokyo JA), Method of removing mercury vapor from gases contaminated therewith.
  15. Katzman James A. (San Jose CA) Bartlett Joel F. (Palo Alto CA) Bixler Richard M. (Sunnyvale CA) Davidow William H. (Atherton CA) Despotakis John A. (Pleasanton CA) Graziano Peter J. (Los Altos CA) Gr, Multiprocessor system.
  16. Piras Giancarlo (Milan ITX), Parallel multiprocessing system for an industrial plant.
  17. Keiles Yoel (Havertown PA), Process control system with backup process controller.
  18. Richter David L. (Plano TX), Processing system with dual buses.
  19. Long James R. (Huntsville AL) Harrill Roy L. (Walton Beach FL), Remote multiplexer terminal with redundant central processor units.
  20. Stiffler, Jack J.; Budwey, Michael J.; Nolan, Jr., James M., Self-checking computer circuitry.
  21. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  22. Davis Guy E. (Martinez CA), System for manually or automatically transferring control between computers without power generation disturbance in an e.

이 특허를 인용한 특허 (19)

  1. Funaki, Satoru; Kiyofuji, Yasuhiro; Suenaga, Masashi; Kokura, Shin; Kobayashi, Eiji; Onozuka, Akihiro; Seki, Yusuke; Shimizu, Toshiki; Tahara, Yukiko; Sugimoto, Yuta, Control apparatus and control method.
  2. Zizzi,Stephen, Encrypting file system.
  3. Marshall Joseph R. ; Langston Dale G., Error detection and fault isolation for lockstep processor systems.
  4. Marshall Joseph R. ; Langston Dale G., Error detection and fault isolation for lockstep processor systems.
  5. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  6. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  7. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  8. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  9. Brady James T., Memory controller with parity generator for an I/O control unit.
  10. Aziz Ashar (Fremont CA), Method and apparatus for a key-management scheme for internet protocols.
  11. Daniels Scott Leonard ; Escamilla Terry Dwain ; Neal Danny Marvin ; Ng Yat Hung, Method and system for checking security of data received by a computer system within a network environment.
  12. Runte Richard M. ; Hubbard Henry ; Dennert R. Bruce, Motorcycle rocker assembly.
  13. Friedman Aharon ; Bozoki Eva, Network security device.
  14. Francis,Kenneth A., Rocker box.
  15. Francis, Kenneth A., Rocker box assembly with reed valve.
  16. Horst Robert W. ; Garcia David J. ; Bunton William Patterson ; Bruckert William F. ; Fowler Daniel L. ; Jones ; Jr. Curtis Willard ; Sonnier David Paul ; Watson William Joel ; Williams Frank A., Self-checked, lock step processor pairs.
  17. Friedman Aharon ; Levy Ben Zion, System and method for preventing a first node from being emulated by another node.
  18. Garnett Paul J.,GBX ; Rowlinson Stephen,GBX ; Oyelakin Femi A.,GBX, Tracking memory page modification in a bridge for a multi-processor system.
  19. Beardsley Brent Cameron (Tucson AZ) Knowlden Ronald Robert (Tucson AZ) Spear Gail Andrea (Tucson AZ), Use of configuration registers to control access to multiple caches and nonvolatile stores.
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