초록 ▼

The device and method disclosed relate to the field of electronic devices and methods enabling the transposition of any even-order square matrix, the elements of which are given in sequence. The goal is to provide for the transposition of sequences of data representing elementary image blocks, witho

The device and method disclosed relate to the field of electronic devices and methods enabling the transposition of any even-order square matrix, the elements of which are given in sequence. The goal is to provide for the transposition of sequences of data representing elementary image blocks, without any duplication of the memory space needed to store an elementary block, in optimizing the two parameters of operating speed and space occupied on silicon. This goal is achieved by a buffer memory divided into two identical storage half-planes, working together with a device for the sequencing of the reading/writing operations, providing simultaneously for a reading operation on one of the storage half-planes and a writing operation on the other half-plane.

대표청구항 ▼

A buffer memory device, particularly for the line/column matrix transposition of word sequences of (n×n) words (n being an even whole number) of the type of elementary image blocks used in digital television, each source sequence being converted into a transposed sequence, wherein said buffer memory

A buffer memory device, particularly for the line/column matrix transposition of word sequences of (n×n) words (n being an even whole number) of the type of elementary image blocks used in digital television, each source sequence being converted into a transposed sequence, wherein said buffer memory is divided into two identical storage half-planes, each provided with individual reading/writing means, and addressing means cooperating with means for sequencing of the reading/writing operations of the storage half-planes, said sequencing means for controlling the execution of a succession of pairs of reading/writing operations, each pair simultaneously comprising a reading operation on one of said storage half-planes, and a writing operation on the other half-plane, said sequencing means comprising means for generating an addressing cycle, said addressing cycle consisting of a successing of two alternated, elementary addressing cycles for the filling and reading of words loaded in the buffer memory, respectively, each source sequence being loaded in alternation, in one and then in the other elementary addressing cycle, the corresponding transposed sequence being read according to the opposite elementary addressing cycle.