초록 ▼

Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding

Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding sites on the surface of the wafer 10, 201 to which chips 11 are bonded to form a hybrid monolithic wafer system. The wafer 10 is packaged within a wafer package, FIG. 4, and the packaging system utilizes a header 20 which is a flexible circuit connector between the wafer package and first level circuit board 30.

대표청구항 ▼

A wafer scale package system, comprising: a substantially rigid wafer based substrate which supports a plurality of integrated circuits, said substrate including a network of electrically conductive lines for selectively interconnecting said circuits together on said substrate, and a plurality of si

A wafer scale package system, comprising: a substantially rigid wafer based substrate which supports a plurality of integrated circuits, said substrate including a network of electrically conductive lines for selectively interconnecting said circuits together on said substrate, and a plurality of sites disposed generally around the periphery of said substrate for enabling external electrical connections to be made with at least some of said lines; a substantially rigid circuit board; and flexible header means disposed generally between the periphery of said substrate and said circuit board for providing a flexible interface between said substrate and said circuit board, said header means having a plurality of inner sites for facilitating selected electrical connections between said substrate and said header means, a plurality of outer sites for facilitating selected electrical connections between said header means and said circuit board, and an electrically conductive line extending between and joining corresponding pairs of said inner and outer sites, and said header means being formed to permit said substrate to move relative to said circuit board in response to relative thermal expansion and contraction of said substrate with respect to said circuit board, so as to permit said substrate to lift slightly from said circuit board in response to a predetermined change in temperature; and wherein said header means has aperture means for permitting a linear lift of said substrate with respect to said circuit board.