초록

In a multiprocessor system with a common bus and a central arbitration controller, which samples the request status of every system agent, the arbitration controller grants bus accesses based on an arbitration scheme consisting of two rotating queues with a fixed priority between the queues.

대표청구항 ▼

A multiprocessor system, comprising: a common bus; a plurality of first system agents connected to the bus and a plurality of second system agents connected to the bus, each system agent having means for selectively generating a request signal to request access to the bus; and central arbitration co

A multiprocessor system, comprising: a common bus; a plurality of first system agents connected to the bus and a plurality of second system agents connected to the bus, each system agent having means for selectively generating a request signal to request access to the bus; and central arbitration controller means for sampling the request signals generated by the system agents and for granting bus access based on an arbitration scheme having a plurality of rotating queues with a fixed priority between the queues, the central arbitration controller means including first latch means for storing request signals generated by the first system agents, first combinatorial logic means, responsive to the signals stored by the first latch means, for selecting the next first system agent to have priority, among the plurality of first system agents, in accessing the bus, and first FIFO memory means for storing a signal identifying a first system agent that was previously selected to have priority among the plurality of first system agents in accessing the bus, wherein the first combinatorial logic means is additionally responsive to the signal stored in the first FIFO memory means.