IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0304069
(1989-01-30)
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발명자
/ 주소 |
- Ngoc Danh Le (Saratoga CA) Mick John R. (Los Altos Hills CA)
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출원인 / 주소 |
- Integrated Device Technology, Inc. (Santa Clara CA 02)
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인용정보 |
피인용 횟수 :
2 인용 특허 :
2 |
초록
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For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register (“A”), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as f
For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register (“A”), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and “delay”the parameter represented by the state of signals externally developed on a “DA”bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for “bit-reverse order”addressing; and a unit for “rounding off”certain results.
대표청구항
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An arithmetic logic system comprising in combination: a DA bus; a DB bus; an R bus; an S bus; a FB bus; a YO bus; pipeline register means including a set of data inputs connected to said DA bus and a set of data outputs connected to said R bus; a B register including a set of data inputs connected t
An arithmetic logic system comprising in combination: a DA bus; a DB bus; an R bus; an S bus; a FB bus; a YO bus; pipeline register means including a set of data inputs connected to said DA bus and a set of data outputs connected to said R bus; a B register including a set of data inputs connected to said DB bus and a set of data outputs; a B multiplexer including a first set of data inputs connected to said DA bus, a second set of data inputs connected to said DB bus, a third set of data inputs connected to said B register set of data outputs, a fourth set of data inputs connected to said FB bus, and a set of data outputs connected to said S bus; an arithmetic logic unit means including a first set of data inputs coupled to said R bus, a second set of data inputs coupled to said S bus, and a set of data outputs; a funnel shifter including a first set of data inputs connected to said R bus, a second set of data inputs connected to said S bus, and a set of data outputs; a merge logic unit including a set of merge left data inputs connected to said funnel shifter set of data outputs, a set of merge mask data/control inputs connected to said S bus, a set of merge right data inputs connected to said FB bus, and a set of data outputs; a funnel shifter/merge logic unit multiplexer including a first set of data inputs connected to said funnel shifter set of data outputs, a second set of data inputs connected to said merge logic unit set of data outputs, and a set of data outputs; an output means connected to said arithmetic logic unit means set of data outputs, to said funnel shifter/merge logic unit multiplexer set of data outputs, to said FB bus, and to said YO bus.
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